[U-Boot] [PATCH v5 22/26] clk: sunxi: Implement SPI clocks

[Jagan Teki]

Implement SPI AHB and MOD clocks for Allwinner A10/A20
and A10s/A13 SoC clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 1b074e3872..2b834856b3 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -18,6 +18,15 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_AHB_OHCI0]         = GATE(0x060, BIT(2)),
        [CLK_AHB_EHCI1]         = GATE(0x060, BIT(3)),
        [CLK_AHB_OHCI1]         = GATE(0x060, BIT(4)),
+       [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
+       [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
+       [CLK_AHB_SPI3]          = GATE(0x060, BIT(23)),
+
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
+       [CLK_SPI3]              = GATE(0x0d4, BIT(31)),
 
        [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
        [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index a50c6e3f7f..0cc48ed2e8 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -16,6 +16,13 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_AHB_OTG]           = GATE(0x060, BIT(0)),
        [CLK_AHB_EHCI]          = GATE(0x060, BIT(1)),
        [CLK_AHB_OHCI]          = GATE(0x060, BIT(2)),
+       [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
+       [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
+
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
 
        [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
        [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
-- 
2.18.0.321.gffc6fa0e3

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