Hi Cédric,
On Wed, 10 Oct 2018 11:46:56 +0530
Jagan Teki wrote:
> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
> >
> > On 10/4/18 5:57 PM, Jagan Teki wrote:
> > > On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater wrote:
> > >>
> > >> Hello Simon,
> > >>
> > >>
> > >> The Aspeed A
Add code to configure PLL4, from which the LDB clock are directly
derived.
Signed-off-by: Marek Vasut
Cc: Stefano Babic
---
V2: Enable config_ldb_clk() for MX53 only by adding ifdef
---
arch/arm/include/asm/arch-mx5/clock.h | 1 +
arch/arm/mach-imx/mx5/clock.c | 29
On 10/09/2018 10:27 PM, Stefano Babic wrote:
> Hi Marek,
>
> On 04/10/2018 21:17, Marek Vasut wrote:
>> Add code to configure PLL4, from which the LDB clock are directly
>> derived.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Stefano Babic
>> ---
>> arch/arm/include/asm/arch-mx5/clock.h | 1 +
>>
On Fri, Oct 5, 2018 at 11:34 AM Patrick Delaunay
wrote:
> The interruption support had be removed for ARM architecture and
> the function get_timer_masked() is no more used except in some
> the timer.c files.
>
> This patch clean each timer.c which implement this function and
> remove the associa
Hi Jagan,
On Wed, Oct 10, 2018 at 11:28:17AM +0530, Jagan Teki wrote:
> On Wed, Oct 10, 2018 at 5:10 AM Angelo Dureghello wrote:
> >
> > Adding DM and DT support and removing old non-DM code.
>
> Commit head can be: spi: cf_spi: Convert to driver model
>
Ok, as you prefer. Will do in v3.
> >
>
On Wed, Oct 10, 2018 at 11:21:45AM +0530, Jagan Teki wrote:
> On Wed, Oct 10, 2018 at 11:14 AM Angelo Dureghello wrote:
> >
>
> Commit message?
>
Ok, will add it, v3 in short.
> > Signed-off-by: Angelo Dureghello
> > ---
> > Changes for v2:
> > - new patch
> > ---
> > drivers/spi/Kconfig | 18
On 10/10/2018 06:26 AM, Simon Goldschmidt wrote:
> This patch prevents disabling the FPGA bridges when
> SPL or U-Boot is executed from FPGA onchip RAM.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v4:
> - use an inline function in misc.h to check for the address
> range instead o
On Wed, Oct 10, 2018 at 12:21 PM Marek Vasut wrote:
>
> On 10/10/2018 06:26 AM, Simon Goldschmidt wrote:
> > This patch prevents disabling the FPGA bridges when
> > SPL or U-Boot is executed from FPGA onchip RAM.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > Changes in v4:
> > - use an
On Wed, Oct 10, 2018 at 11:19:26AM +0530, Jagan Teki wrote:
> On Wed, Oct 10, 2018 at 5:09 AM Angelo Dureghello wrote:
> >
> > This patch adds a basic group of devicetrees, one for each
> > cpu family, including actually just uart and dspi devices,
> > since these are the drivers supporting device
On 10/10/2018 12:32 PM, Simon Goldschmidt wrote:
> On Wed, Oct 10, 2018 at 12:21 PM Marek Vasut wrote:
>>
>> On 10/10/2018 06:26 AM, Simon Goldschmidt wrote:
>>> This patch prevents disabling the FPGA bridges when
>>> SPL or U-Boot is executed from FPGA onchip RAM.
>>>
>>> Signed-off-by: Simon Gol
On 10/10/2018 12:49 PM, Marek Vasut wrote:
> On 10/10/2018 12:32 PM, Simon Goldschmidt wrote:
>> On Wed, Oct 10, 2018 at 12:21 PM Marek Vasut wrote:
>>>
>>> On 10/10/2018 06:26 AM, Simon Goldschmidt wrote:
This patch prevents disabling the FPGA bridges when
SPL or U-Boot is executed from
> -Original Message-
> From: Jagan Teki
> Sent: Wednesday, October 10, 2018 11:51 AM
> To: Ashish Kumar
> Cc: U-Boot-Denx ; Jagan Teki ;
> Rajat Srivastava ; Suresh Gupta
>
> Subject: Re: [U-Boot] [PATCH] driver/mtd: Add MICRON manufacturer id in spi
> framework
>
> On Tue, Sep 25, 2018
On Wed, Oct 10, 2018 at 12:50 PM Marek Vasut wrote:
>
> On 10/10/2018 12:49 PM, Marek Vasut wrote:
> > On 10/10/2018 12:32 PM, Simon Goldschmidt wrote:
> >> On Wed, Oct 10, 2018 at 12:21 PM Marek Vasut wrote:
> >>>
> >>> On 10/10/2018 06:26 AM, Simon Goldschmidt wrote:
> This patch prevents
Hi Jagan,
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ashish
> Kumar
> Sent: Wednesday, October 10, 2018 4:23 PM
> To: Jagan Teki
> Cc: U-Boot-Denx ; Jagan Teki ;
> Rajat Srivastava ; Suresh Gupta
>
> Subject: Re: [U-Boot] [PATCH] driver/mtd: Ad
Hello,
This series re-enables the Faraday ftgmac100 controller driver and its
Aspeed variant as as one can find on the OpenPOWER platforms. The
driver is largely reworked to support the driver model and also adds
the MDIO bus and phylib support. It was tested on the AST2500 evb.
Git tree availabl
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.h | 154
1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index ffbe1f3e3fa7..439b14d71e4b 100644
--- a/drivers/net/ftgmac100.h
+++ b
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index 439b14d71e4b..9a789e4d5bee 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -182,7 +182,
Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.c | 380 +---
1 file changed, 159 insertio
The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.
Configuration is updated to enable compile again. At this stage, the
driver compiles but is
The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.
This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Simon Glass
---
drivers/clk/aspeed/clk_ast2500.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..2182320f607f 100644
--- a/drivers/c
Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.
Signed-off-by: Cédric Le Goater
---
At this stage, the drive is functional.
drivers/net/ftgmac100.c | 141 ++-
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index b46187b567c6..edf34c601c68 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -28,6 +28,9
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 67a7c73503c5..78cd9df62986 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -331,7 +331,7 @@
Signed-off-by: Cédric Le Goater
---
drivers/net/ftgmac100.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index edf34c601c68..a5f2f01b7179 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@
This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :
Author: Joel Stanley
Date:Sat Jun 2 01:18:53 2018 -0700
ARM: dts: aspeed: Fix hwrng register address
There are some differences on the compatibility property names. scu,
re
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
Signed-off-by: Cédric Le Goater
Reviewed-by: Simon Glass
---
drivers/net/ftgmac100.c | 31 +++
configs/evb-ast2500_defco
Signed-off-by: Cédric Le Goater
Reviewed-by: Simon Glass
---
arch/arm/dts/ast2500-evb.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0bee..ebf44fd707f9 100644
--- a/arch/arm/dts/ast2500-ev
Hello Boris,
On 10/10/18 9:32 AM, Boris Brezillon wrote:
> Hi Cédric,
>
> On Wed, 10 Oct 2018 11:46:56 +0530
> Jagan Teki wrote:
>
>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
>>>
>>> On 10/4/18 5:57 PM, Jagan Teki wrote:
On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater w
This patch prevents disabling the FPGA bridges when
SPL or U-Boot is executed from FPGA onchip RAM.
Signed-off-by: Simon Goldschmidt
---
Changes in v5:
- changed inline function 'socfpga_is_fpga_slaves_addr(addr)'
to 'socfpga_is_booting_from_fpga()'
Changes in v4:
- use an inline function in
Hi Jagan,
Jagan Teki wrote on Wed, 10 Oct 2018
11:32:02 +0530:
> On Tue, Oct 9, 2018 at 12:43 AM Adam Ford wrote:
> >
> > Some boards (like omap3_logic) hang when trying to access
> > address 0. This happens when executing the new 'mtd list' command.
> > This patch enhances the checks for condi
On Wed, Oct 10, 2018 at 6:39 PM Miquel Raynal wrote:
>
> Hi Jagan,
>
> Jagan Teki wrote on Wed, 10 Oct 2018
> 11:32:02 +0530:
>
> > On Tue, Oct 9, 2018 at 12:43 AM Adam Ford wrote:
> > >
> > > Some boards (like omap3_logic) hang when trying to access
> > > address 0. This happens when executing
Hi Jagan,
Jagan Teki wrote on Wed, 10 Oct 2018
18:41:39 +0530:
> On Wed, Oct 10, 2018 at 6:39 PM Miquel Raynal
> wrote:
> >
> > Hi Jagan,
> >
> > Jagan Teki wrote on Wed, 10 Oct 2018
> > 11:32:02 +0530:
> >
> > > On Tue, Oct 9, 2018 at 12:43 AM Adam Ford wrote:
> > > >
> > > > Some board
+ Marek (as he commented on the original patch
http://patchwork.ozlabs.org/patch/955765/)
On 09.10.2018 07:06, Simon Goldschmidt wrote:
On Tue, Oct 9, 2018 at 5:41 AM Simon Glass wrote:
Hi,
On 7 October 2018 at 11:52, Simon Goldschmidt
wrote:
At least on socfpga gen5, _debug_uart_putc() ca
Hi Simon,
On Wed, Oct 10, 2018 at 12:20 AM Simon Glass wrote:
>
> Hi Bin,
>
> On 4 October 2018 at 01:00, Bin Meng wrote:
> > Hi Simon,
> >
> > On Tue, Oct 2, 2018 at 7:22 PM Simon Glass wrote:
> >>
> >> Hi,
> >>
> >> On 27 September 2018 at 15:19, Tuomas Tynkkynen
> >> wrote:
> >> > Hi Simon
Enable modern fitImage format on sunxi.
Signed-off-by: Marek Vasut
Cc: Maxime Ripard
Cc: Tom Rini
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8a23c76db8..0f7829595a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -8
I am wondering if anyone has done any tests using LTO in SPL? For
those of us with limited resources, I noticed that we're creeping up
in size, especially when using DM in SPL.
I made a few attempts to enable -flto during compile, but the .S files
fail to assemble. I found some references that i
This commit broke our pca953x usage(on ppc).
I wonder why gpio pins here has an endian, its not a number.
If there must be an endian connected with this, should it not
be a cpu_to_be16 instead, which will retain compatibility ?
___
U-Boot mailing list
U-
On Wed, Oct 10, 2018 at 12:11 AM Pankaj Bansal wrote:
>
> Hi Joe,
>
> > -Original Message-
> > From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> > Sent: Wednesday, October 10, 2018 9:29 AM
> > To: Pankaj Bansal
> > Cc: Joseph Hershberger ; u-boot > b...@lists.denx.de>
> > Subject:
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. conf
Add PCI entry without compatible string and with a DT node only with
reg = <...> property into the DT. This is needed for the tests to
verify whether such a setup creates an U-Boot PCI device with the
DT node associated with it in udevice.node.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom
Reword the documentation to make it clear the compatible string is now
optional, yet still matching on it takes precedence over PCI IDs and
PCI classes.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom Rini
---
doc/driver-model/pci-info.txt | 14 +-
1 file changed, 9 insertions(+
Add test which checks if a PCI device described in DT with an
entry and reg = <...> property, but without compatible string
results in a valid U-Boot PCI udevice with the udevice.node
populated with reference to this DT node. Also check if the
other PCI device without a DT node does not contain any
Hi Simon,
On 10 October 2018 at 07:28, Simon Goldschmidt
wrote:
>
> + Marek (as he commented on the original patch
> http://patchwork.ozlabs.org/patch/955765/)
>
> On 09.10.2018 07:06, Simon Goldschmidt wrote:
>>
>> On Tue, Oct 9, 2018 at 5:41 AM Simon Glass wrote:
>>>
>>> Hi,
>>>
>>> On 7 Octo
On Wed, Oct 10, 2018 at 10:03 PM Simon Glass wrote:
>
> Hi Simon,
>
> On 10 October 2018 at 07:28, Simon Goldschmidt
> wrote:
> >
> > + Marek (as he commented on the original patch
> > http://patchwork.ozlabs.org/patch/955765/)
> >
> > On 09.10.2018 07:06, Simon Goldschmidt wrote:
> >>
> >> On T
On 10/10/2018 07:30 AM, Ang, Chee Hong wrote:
> On Tue, 2018-10-09 at 14:48 +0200, Marek Vasut wrote:
>> On 10/09/2018 05:03 AM, Ang, Chee Hong wrote:
>>>
>>> On Mon, 2018-10-08 at 22:32 +0200, Marek Vasut wrote:
On 10/08/2018 05:10 PM, Ang, Chee Hong wrote:
>
>
> On Mon, 2018
On 10/10/2018 02:55 PM, Simon Goldschmidt wrote:
> This patch prevents disabling the FPGA bridges when
> SPL or U-Boot is executed from FPGA onchip RAM.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v5:
> - changed inline function 'socfpga_is_fpga_slaves_addr(addr)'
> to 'socfpga_i
Add new Kconfig option, SYS_BOOTCOUNT_MAGIC, to select the boot
counter magic word. This can be useful ie. in case the entire
boot counter register is not usable.
Signed-off-by: Marek Vasut
Cc: Tom Rini
---
drivers/bootcount/Kconfig | 6 ++
drivers/bootcount/bootcount.c
Compiling the overlay unit test fails with odroid-c2_defconfig showing
errors like:
test/overlay/cmd_ut_overlay.c:29:8:
error: unknown type name ‘fdt32_t’
Add the missing include.
Signed-off-by: Heinrich Schuchardt
---
test/overlay/cmd_ut_overlay.c | 1 +
1 file changed, 1 insertion(+)
On 10 October 2018 at 18:16, Heinrich Schuchardt wrote:
>
> Compiling the overlay unit test fails with odroid-c2_defconfig showing
> errors like:
>
> test/overlay/cmd_ut_overlay.c:29:8:
> error: unknown type name ‘fdt32_t’
>
> Add the missing include.
>
> Signed-off-by: Heinrich Schuchardt
With the '-march=core2' fix, it seems that we have some luck that
the 64-bit U-Boot boots again. However if we examine the disassembly
codes there are still SSE instructions elsewhere which means passing
cpu type to GCC is not enough to prevent it from generating these
instructions. A simple test c
With newer kernel.org GCC (7.3.0 or 8.1.0), the u-boot.rom image
built for qemu-x86_64 target does not boot. It keeps resetting
soon after the 32-bit SPL jumps to 64-bit proper. Debugging shows
that the reset happens inside env_callback_init().
0113dd85 :
113dd85: 41 54
Add qemu-x86_64 to the list of targets we use for test.py runs.
Signed-off-by: Bin Meng
---
testp.py testing is currently failing at 'bootefi selftest'.
.travis.yml | 8
1 file changed, 8 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 2b759c9..9d0531f 100644
--- a/.travis
Currently only 32-bit U-Boot for QEMU x86 is documented. Mention
the 64-bit support.
Signed-off-by: Bin Meng
---
doc/README.x86 | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86
index 8cc4672..ab48466 100644
--- a/doc/README.x86
+++ b/do
Hi Bin,
On 6 October 2018 at 10:32, Bin Meng wrote:
> On Sat, Oct 6, 2018 at 9:14 PM Bin Meng wrote:
>>
>> Hi Simon,
>>
>> With current u-boot/master, there are 4 failures with 'ut dm'. I was
>> wondering is this not covered by travis-ci?
>>
>> Test: dm_test_bus_children: bus.c
>> test/dm/bus.c:
Hi Heinrich,
On Thu, Oct 11, 2018 at 9:48 AM Bin Meng wrote:
>
> Add qemu-x86_64 to the list of targets we use for test.py runs.
>
> Signed-off-by: Bin Meng
>
> ---
> testp.py testing is currently failing at 'bootefi selftest'.
>
Can you try this series for the 'bootefi selftest' testing?
BTW:
On 7 October 2018 at 04:01, Bin Meng wrote:
> It was observed that current output of print_cpuinfo() on QEMU
> x86 targets does not have an ending '\n', neither have a leading
> 'CPU:' any more. However it used to have these before.
>
> It turns out commit c0434407b595 introduced a unified DM vers
On 7 October 2018 at 04:01, Bin Meng wrote:
> This adds a new API dm_ofnode_pre_reloc(), a livetree equivalent
> API of dm_fdt_pre_reloc().
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> drivers/core/util.c | 25 +
> include/dm/util.h | 27 +++
On 7 October 2018 at 04:01, Bin Meng wrote:
> Currently the comments of several APIs (eg: dm_init_and_scan()) say:
>
> @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
> flag. If false bind all drivers.
>
> The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt
>
On 7 October 2018 at 04:01, Bin Meng wrote:
> The description string should not contain unnecessary characters,
> like the ending '\n' or the leading 'CPU:'.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> drivers/cpu/mpc83xx_cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deleti
On 7 October 2018 at 04:01, Bin Meng wrote:
> The pre_reloc_only parameter description currently only mentions
> drivers with the DM_FLAG_PRE_RELOC flag, but does not mention the
> special device tree properties. Correct them.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> include
On 7 October 2018 at 04:01, Bin Meng wrote:
> This is currently out of order. Sort it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2: None
>
> drivers/timer/Kconfig | 110
> +-
> 1 file changed, 55 insertions(+), 55 deletions(-)
Reviewed-
On 7 October 2018 at 04:01, Bin Meng wrote:
> Commit f2006808f099: ("dm: core: parse chosen node") added a logic
> to parse the chosen node during dm_scan_fdt_node(), but unfortunately
> it missed adding the same logic in dm_scan_fdt_live(). This mirrors
> the logic in the livetree version.
>
> Th
On 7 October 2018 at 04:01, Bin Meng wrote:
> Now that we fixed the pre-relocation driver binding for driver marked
> with DM_FLAG_PRE_RELOC flag, add a test case to cover that scenario.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/sandbox/dts/test.dts | 4
> test/dm/
Hi Simon,
On Thu, Oct 11, 2018 at 10:01 AM Simon Glass wrote:
>
> On 7 October 2018 at 04:01, Bin Meng wrote:
> > This adds a new API dm_ofnode_pre_reloc(), a livetree equivalent
> > API of dm_fdt_pre_reloc().
> >
> > Signed-off-by: Bin Meng
> > ---
> >
> > Changes in v2: None
> >
> > drivers/
Hi Jean-Jacques,
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> In a non-DM environment, it is possible to test the presence of a chip
> using i2c_probe(chip_addr).
> dm_i2c_probe_device() brings the same functionality with a DM interface.
> The intent is to be able to test the presence
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> The implementation of the EEPROM commands does not support the DM I2C API.
> Prevent compilation breakage by not enabling it if the non-DM API is not
> available (if DM_I2C is used without DM_I2C_COMPAT)
>
> Signed-off-by: Jean-Jacques Hiblo
Hi Jean-Jacques,
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> In some cases it may be useful to be able to change the fdt we have been
> using and use another one instead. For example, the TI platforms uses an
> EEPROM to store board information and, based on the type of board,
> diff
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> Changes in v2: None
>
> arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 4
> arch/arm/dts/omap5-u-boot.dtsi | 4
> 2 files changed, 8 insertions(+)
Reviewed-by: Simon Glass
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> Changes in v2: None
>
> drivers/core/Kconfig | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
But please always add a commit message:
- motivati
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> If OF_CONTROL is not enabled and DM_SEQ_ALIAS is enabled, we must
> assign an alias (requested sequence number) to devices that belongs to a
> class with the DM_UC_FLAG_SEQ_ALIAS flag. Otherwise
> uclass_find_device_by_seq() cannot be used t
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
> To reset the DM after a new dtb is loaded, we need to call dm_uninit()
> and then dm_init(). This fails however because gd->dm_root is not nullified
> by dm_uninit().
> Fixing it by setting gd->dm_root in dm_uninit().
>
> Signed-off-by: Jean
On 10 October 2018 at 00:28, Andy Yan wrote:
> Hi Simon:
>
> Simon Glass 于2018年8月30日周四 上午8:42写道：
>>
>> On 7 August 2018 at 05:44, Andy Yan wrote:
>> > Memory region for fdt should be reserved, or they
>> > may be allocated by other module via lmb_alloc.
>> > Then the fdt data will be destroy.
>>
On Thu, Oct 11, 2018 at 3:27 AM Marek Vasut wrote:
>
> The PCI controller can have DT subnodes describing extra properties
> of particular PCI devices, ie. a PHY attached to an EHCI controller
> on a PCI bus. This patch parses those DT subnodes and assigns a node
> to the PCI device instance, so t
Hi Marek,
On Thu, Oct 11, 2018 at 3:28 AM Marek Vasut wrote:
>
> Reword the documentation to make it clear the compatible string is now
> optional, yet still matching on it takes precedence over PCI IDs and
> PCI classes.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> ---
>
On Thu, Oct 11, 2018 at 3:28 AM Marek Vasut wrote:
>
> Add PCI entry without compatible string and with a DT node only with
> reg = <...> property into the DT. This is needed for the tests to
> verify whether such a setup creates an U-Boot PCI device with the
> DT node associated with it in udevic
On Thu, Oct 11, 2018 at 3:29 AM Marek Vasut wrote:
>
> Add test which checks if a PCI device described in DT with an
> entry and reg = <...> property, but without compatible string
> results in a valid U-Boot PCI udevice with the udevice.node
> populated with reference to this DT node. Also check
When starting an aarch64 system under QEMU it runs in EL1/EL0. So we have
to use HVC for PSCI calls.
Without the patch resetting Linux started with bootefi under
qemu-system-aarch64 results in a crash.
Signed-off-by: Heinrich Schuchardt
---
arch/arm/cpu/armv8/fwcall.c | 14 +-
1 fil
The 'el' command displays the current exception level of the processor
on the aarch64 architecture.
This information is needed to analyze problems in the EFI subsystem.
Signed-off-by: Heinrich Schuchardt
---
cmd/Kconfig | 7 +++
cmd/Makefile | 1 +
cmd/el.c | 25 +
Signed-off-by: Priyanka Jain
---
include/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/phy.h b/include/phy.h
index 52bf997..ef5ca7e 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -315,5 +315,6 @@ static inline bool phy_interface_is_sgmii(struct phy_device
*phydev)
/* PHY
This fixed several issues identified in dm core/cpu/timer codes.
The issues were found during RISC-V cpu/timer driver development
for QEMU RISC-V port.
This series is available at u-boot-x86/dm-fixes for testing.
Changes in v3:
- rebase on u-boot/master so that patch [4/8] can be applied cleanly
The description string should not contain unnecessary characters,
like the ending '\n' or the leading 'CPU:'.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/cpu/mpc83xx_cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
It was observed that current output of print_cpuinfo() on QEMU
x86 targets does not have an ending '\n', neither have a leading
'CPU:' any more. However it used to have these before.
It turns out commit c0434407b595 introduced a unified DM version
of print_cpuinfo() that exposed such issue on QEMU
Commit f2006808f099: ("dm: core: parse chosen node") added a logic
to parse the chosen node during dm_scan_fdt_node(), but unfortunately
it missed adding the same logic in dm_scan_fdt_live(). This mirrors
the logic in the livetree version.
The weird thing is that commit f2006808f099 did update the
The pre_reloc_only parameter description currently only mentions
drivers with the DM_FLAG_PRE_RELOC flag, but does not mention the
special device tree properties. Correct them.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/dm/device-inter
This is currently out of order. Sort it.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
Changes in v3:
- rebase on u-boot/master so that patch [4/8] can be applied cleanly
Changes in v2: None
drivers/timer/Kconfig | 110 +-
1 file change
This adds a new API dm_ofnode_pre_reloc(), a livetree equivalent
API of dm_fdt_pre_reloc().
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/core/util.c | 25 +
include/dm/util.h | 27 ++-
2
Currently the comments of several APIs (eg: dm_init_and_scan()) say:
@pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
flag. If false bind all drivers.
The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt
documents the same that both device tree properties and
Now that we fixed the pre-relocation driver binding for driver marked
with DM_FLAG_PRE_RELOC flag, add a test case to cover that scenario.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/sandbox/dts/test.dts | 4
test/dm/bus.c
Voltage regulator LTC3882 device has 0.5% voltage read error.
So for NXP SoC devices this generally equates to 2mV
Update set_voltage_to_LTC for below:
1.Add coorection of upto 2mV in voltage comparison
to take care of voltage read error of voltage regulator
2.Add loop max count kept as 100 to a
Hi Simon,
On Thu, Sep 27, 2018 at 9:42 PM Simon Glass wrote:
>
> Hi Bin,
>
> On 23 September 2018 at 06:41, Bin Meng wrote:
> > Some buses need to set up their child devices after they are probed.
> > Support a common child_post_probe() method for the uclass.
> >
> > With this change, the two AP
Signed-off-by: Priyanka Jain
---
board/freescale/common/vid.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index eb5cf88..8d90135 100644
--- a/board/freescale/common/vid.c
+++ b/board/freesca
On Wed, Oct 10, 2018 at 11:47 PM Priyanka Jain wrote:
>
> Signed-off-by: Priyanka Jain
> ---
> include/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/phy.h b/include/phy.h
> index 52bf997..ef5ca7e 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -315,5 +315,6 @@ st
accidentially while fixing merge errors for patch:
https://lists.denx.de/pipermail/u-boot/2018-September/342278.html
missed to add files:
MAINTAINERS
drivers/i2c/Kconfig
drivers/i2c/Makefile
add them with this patch.
Signed-off-by: Heiko Schocher
---
MAINTAINERS | 1 +
drivers/i2c/K
>-Original Message-
>From: Joe Hershberger
>Sent: Thursday, October 11, 2018 10:55 AM
>To: Priyanka Jain
>Cc: u-boot ; York Sun ; Joseph
>Hershberger
>Subject: Re: [U-Boot] [PATCH] net/phy: Add phy-id for IN112525_S03
>
>On Wed, Oct 10, 2018 at 11:47 PM Priyanka Jain
>wrote:
>>
>> Sig
This commit ports the existing (non-DM) function for writing the MAC-
address into the shadow ram (and flash) for DM.
Signed-off-by: Hannes Schmelzer
---
drivers/net/e1000.c | 89 +
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git
Hello Joakim,
Am 10.10.2018 um 19:34 schrieb Joakim Tjernlund:
This commit broke our pca953x usage(on ppc).
I wonder why gpio pins here has an endian, its not a number.
If there must be an endian connected with this, should it not
be a cpu_to_be16 instead, which will retain compatibility ?
Hm
Once we get a zero pointer from load_zimage(...) we must bunch out
instead of continue boot.
Signed-off-by: Hannes Schmelzer
---
arch/x86/lib/bootm.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 54c22fe..832b1f9 100644
--- a/arch/x86/
If we're booting some u-boot module with compressed payload, we have to
use the pointer where the image really has been loaded (unzipped) to
instead the pointer to the payload of the u-boot module.
Signed-off-by: Hannes Schmelzer
---
arch/x86/lib/bootm.c | 4 ++--
1 file changed, 2 insertions(+
On Wed, Oct 10, 2018 at 11:47 PM Priyanka Jain wrote:
>
> Signed-off-by: Priyanka Jain
Acked-by: Joe Hershberger
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