This fixes an issue which has been noticed on the Gardena board, with
the watchdog enabled, where the watdchdog reset (after a system hang)
did result in reporting of 2.9 GiB and a hang after this. With this
patch applied the memory controller is correctly reset and initialized
again even after a w
Using CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD should ensure that the cache
is initialized correctly (parity etc). Even though some issues are
still seen on the linkit and gardena MT7688 platforms, which could
be a result of a non-optimal cache configuration / setup.
Signed-off-by: Stefan Roese
Cc: Da
Add the GPIO DT nodes to the DTS file.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/dts/mt7628a.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index effb36681f..8da2ca3e4d 100
This patch enables and starts the watchdog on the MT7620 platform.
Currently the WD timeout is configured to 60 seconds.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/Kconfig | 1 +
arch/mips/mach-mt7620/cpu.c | 40 +
2 files cha
Configure digital vs analog GPIOs as needed on this board.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
board/gardena/smart-gateway-mt7688/board.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/gardena/smart-gateway-mt7688/board.c
b/board/ga
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI support
- Enable GPIO support
- Change max image size from 0x4 to 0x8
A note about the baudrate change:
Th
in_le32() and out_le32() are needed for the bootcounter support.
So lets implement these accessor functions for MIPS as well.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/include/asm/io.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/mips/in
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI NOR and NAND support
- Change MTD_UBI_BEB_LIMIT to 22
- Enable MTD Support
- Enable GPIO support
- Enable watchdog s
Use the correct function to get the uncached address to access the SoC
registers.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
board/seeed/linkit-smart-7688/board.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/board/seeed/linkit-smart-7688/board.c
b/boar
Add the available LEDs to the DTS file so that they can be used.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
.../mips/dts/gardena-smart-gateway-mt7688.dts | 59 +++
1 file changed, 59 insertions(+)
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
b/arch/m
Add the watchdog DT node to the DTS file.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/dts/mt7628a.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 8da2ca3e4d..70e34cfdbc 100644
--- a/arch/mip
This is needed to set the LEDs automatically to a default state, as
configured in the dts.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/mach-mt7620/Kconfig | 1 +
board/gardena/smart-gateway-mt7688/board.c | 9 +
2 files changed, 10 insertions(+)
diff -
Imply DM_ETH and DM_GPIO for ARCH_MT7620, as this platform now supports
ethernet and GPIO as well.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 071dea04ec..0aa23981d4 10
On Tue, Oct 9, 2018 at 4:49 AM Marek Vasut wrote:
>
> On 10/08/2018 08:26 PM, Simon Goldschmidt wrote:
> > This patch prevents disabling the FPGA bridges when
> > SPL or U-Boot is executed from FPGA onchip RAM.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > Changes in v2:
> > - use less
Only PPC supports this option that's why there should be proper
dependency setup via Kconfig.
Signed-off-by: Michal Simek
---
cmd/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 7ed3c9c3b30b..d66f710ad0f8 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@
From: Marcel Ziswiler
The imx_ddr_size() function may overflow as it is possible to kind of
over provision the DDR controller. Fix this by capping it to 2 GB which
is the maximum allowed size as per reference manual.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Fabio Estevam
---
Changes in v2
From: Fabio Estevam
Rather than passing a hardcoded maxsize to the generic get_ram_size()
function use the i.MX 7 specific imx_ddr_size() function, which extracts
the memory size at runtime by reading the DDR controller registers.
This is a purely cosmetic change as the generic get_ram_size() fu
On Fri, Oct 05, 2018 at 03:06:52PM +0200, Alexander Graf wrote:
> On 10/05/2018 11:49 AM, Leif Lindholm wrote:
> >On Fri, Oct 05, 2018 at 05:52:09PM +0900, AKASHI, Takahiro wrote:
> 2. If a platform includes a configuration infrastructure, then the
> EFI_HII_DATABASE_PROTOCOL, EFI_HII_STRIN
Hi sir,
i am using ZYNQ ZC706 Board and i have downloaded
u-boot(2016.7),uImage,root file system files from wiki.xilinx.com website
downloaded and properly working all the things.
But i am doing manually downloaded u-boot from github and ELDK-5.5.3
version taken
export
PATH=/opt/eldk-5.5.3/armv7a-
Hi Bin,
Bin Meng wrote on Mon, 8 Oct 2018 02:27:44 -0700:
> Currently in pmecc_get_sigma(), the code tries to clear the memory
> pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
> Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu)
> does not generate correct si
Hi Simon and Bin,
Do I need to send the standalone patch 1/2 in version 2?
Thanks,
Zhiqiang
> -Original Message-
> From: s...@google.com On Behalf Of Simon Glass
> Sent: 2018年10月9日 11:41
> To: Bin Meng
> Cc: Z.q. Hou ; U-Boot Mailing List
> ; Christian Gmeiner ;
> Tuomas Tynkkynen ; Be
> -Original Message-
> From: York Sun
> Sent: Monday, October 8, 2018 10:11 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha
> Subject: Re: [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms
>
> On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
> > Includes
> -Original Message-
> From: York Sun
> Sent: Monday, October 8, 2018 8:35 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Pankit Garg
>
> Subject: Re: [PATCH v2 21/33] armv8: ls1046ardb: Add TFABOOT support
>
> On 10/07/2018 03:22 AM, Rajesh Bhagat wrote:
> > T
> -Original Message-
> From: York Sun
> Sent: Monday, October 8, 2018 8:08 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha
> Subject: Re: [PATCH v2 01/33] move data structure out of cpu.h
>
> On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
> > From: York Sun
> >
> >
> -Original Message-
> From: York Sun
> Sent: Monday, October 8, 2018 8:19 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha
> Subject: Re: [PATCH v2 10/33] armv8: layerscape: remove EL3 specific erratas
> for TFABOOT
>
> On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
If the kernel is on an ext partition, we cannot load it because
spl_boot_mode() return MMCSD_MODE_RAW instead of MMCSD_MODE_FS.
Signed-off-by: Fabien Lahoudere
---
arch/arm/mach-imx/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-
Hi Michal
On 10/08/2018 08:28 AM, Michal Simek wrote:
> On 6.10.2018 15:33, Patrice CHOTARD wrote:
>> Hi
>>
>> I got same issue on STM32F746
>
> Will be good to convert this to more formal line to have a record in git
> commit.
commit c35a7d375ec8f0a8ee343ae4868be3242172632e breaks also the SPL
Hi Heinrich,
Did you ever get 'bootefi selftest' pass on qemu-x86_64? I got:
=> bootefi selftest
WARNING: booting without device tree
lib/efi_selftest/efi_selftest.c(242):
ERROR: Cannot open loaded image protocol
Regards,
Bin
___
U-Boot mailing list
U-
Hi Eugen
On 10/01/2018 03:26 PM, Eugen Hristev wrote:
>
>
> On 01.10.2018 14:59, Patrice Chotard wrote:
>> Add get_pin_mux ops support to display the pin muxing
>> description of the sandbox_pins[]
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> Changes in v2: None
>>
>> drivers/pinctrl/pin
There's no Ethernet controller on the board so no point in having
networking support. This also saves us 5.5 kB of precious memory.
| # bloat-o-meter u-boot.net u-boot.no_net_regex | tail -1
| Total: Before=127892, After=122334, chg -4.35%
Signed-off-by: Alexey Brodkin
---
configs/iot_devkit_de
Includes changes in u-boot framework to support TF-A for NXP Chassis 2
platforms. A new defconfig is added namely ls*_tfa_defconfig which will
be used for all boot sources when TF-A is used.
From: York Sun
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +
.../arm/include/asm/arch-fsl-la
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
env/sf.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 494
Define env_ptr as static in flash and nand env driver to
allow these to compile together.
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Merged env nand specific patches to remove compilation warning
Change in v2: None
env/flash.c | 4 ++--
env/nand.c| 6 ++
includ
From: Pankit Garg
IFC driver changes to implement the chipselect mappings at run time.
Defines init_early_memctl_regs and init_final_memctl_regs with
chipselect dynamic mapping for nor and nand boot.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2:
From: Pankit Garg
Change tlb base address from OCRAM to DDR when exception level is
less than 3.
Signed-off-by: Ruchika Gupta
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Replaces __ilog2 function call with LOG2 macro, required to
use macros in global variables.
Also, corrects the value passed in LOG2 for some PowerPC
platforms. Minimum value that can be configured is is 64K
for IFC IP.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: No
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.
Signed-off-by: Ruchika Gupta
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlev
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803
SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat
---
Ch
From: York Sun
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/arm
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17,
it is applicable to both TFA and non-TFA boot.
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/a
Adds TFABOOT support config option and add generic code to enable
execution from DDR.
Signed-off-by: York Sun
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Seperated TFABOOT generic code
- Moved before dependency patches
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
arch/arm/cpu/
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1
TFABOOT support includes:
- ls1012aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat
Signed-off-by: Vinitha V Pillai
Signed-off-by: Pankit Garg
---
Change in v3:
TFABOOT support includes:
- ls1012ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat
Signed-off-by: Vinitha V Pillai
Signed-off-by: Pankit Garg
---
Change in v3:
TFABOOT support includes:
- ls1046ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Sig
From: York Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erra
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
TFABOOT support includes:
- ls1043ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN and QE address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2:
- Removed extra CONFIG_TFABOOT flag usage
drivers/n
From: Pankit Garg
Add support of MC framework for TFA
Make MC framework independent of boot source.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 50 +
1 file changed, 50 ins
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
2 files
From: Pankit Garg
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.
Signed-off-by: Ruchika Gupta
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/sec_firmware.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/a
From: Pankit Garg
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3:
- Merged secure boot bootcmd changes
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +
arch/
TFABOOT support includes:
- ls1043aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
---
Change in v3:
From: Vinitha V Pillai
Includes environment.h file in ls1012aqds.c Also, enables
pfe validation in ls1012ardb.
Signed-off-by: Vinitha V Pillai
---
Change in v3: None
Change in v2: None
board/freescale/ls1012aqds/Kconfig | 10 ++
board/freescale/ls1012aqds/ls1012aqds.c |
On 09.10.2018 06:40, Simon Glass wrote:
> Hi Eugen,
>
> On 2 October 2018 at 01:37, Eugen Hristev wrote:
>>
>>
>>
>> On 01.10.2018 23:22, Anatolij Gustschin wrote:
>>>
>>> Hi Simon,
>>>
>>> On Mon, 1 Oct 2018 12:22:47 -0600
>>> Simon Glass s...@chromium.org wrote:
>>>
At present this func
TFABOOT support includes:
- ls1046aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
Hi Patrice,
On 9.10.2018 11:15, Patrice CHOTARD wrote:
> Hi Michal
>
> On 10/08/2018 08:28 AM, Michal Simek wrote:
>> On 6.10.2018 15:33, Patrice CHOTARD wrote:
>>> Hi
>>>
>>> I got same issue on STM32F746
>>
>> Will be good to convert this to more formal line to have a record in git
>> commit.
>
Hi Daniel,
I am bout to send a new version of the series, but befor I am going to
answer to the pending point I didn't already address in my email 10 days
ago.
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> Hi Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> These families of
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
[...]
>> diff --git a/board/mscc/ocelot/Kconfig b/board
The CPLD is used to reset the ULCB and it was removed
during DT sync with Linux 4.17. Reinstate it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/ulcb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
index bff0
Hi Marek,
On jeu., sept. 27 2018, Marek Vasut wrote:
> On 09/25/2018 03:01 PM, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> board/mscc/common
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding device tree for Ocelot SoC (extract from Linux) and the 2
>> evaluation boards using this SoC: PCB120 and PCB132.
>>
>> Adding device tree for Luton SoC (not yet in Linux) and
Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
so we don't have to apply casts throughout the code.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
---
drivers/mmc/tmio-common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/tmio-common.c
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Add common configuration header for the VCore III SoCs (currently Ocelot
>> and Luton), but also the defconfig for the evaluation boards of these
>> SoCs.
>>
>> Signed-off-by: Gregor
The internal DMAC on Gen3 is 32bit only, limit the DMA address
range to 32bit.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
---
drivers/mmc/tmio-common.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 6b21941991..138de5947
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single s
On Mon, Oct 8, 2018 at 4:36 AM Jean-Jacques Hiblot wrote:
>
>
>
> On 06/10/2018 03:22, Adam Ford wrote:
> > On Thu, Oct 4, 2018 at 8:48 AM Jean-Jacques Hiblot wrote:
> >> This series remove the usage of the DM_I2C_COMPAT option for all the ti
> >> platforms. It also takes this opportunity to not
Avoid "SF: Timeout!" messages and generally speed up QSPI flash
operations on mx6ull EVK by adding a QSPI sequence for reading
"flag status register" as required for some (ST/Micron) NOR
flash devices by the DM spi-flash driver.
Enable QSPI clock in EVK specific board_init function, as per
other
Hi Kever,
On 7 October 2018 at 20:30, Kever Yang wrote:
>
> Hi Simon,
>
>
> On 09/27/2018 05:54 AM, Simon Glass wrote:
> > At present we have no standard way of passing information from SPL to
> > U-Boot. Such information may be the size of DRAM banks or some information
> > about the reset state
On Mon, Oct 08, 2018 at 09:40:51PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 7 October 2018 at 12:20, Tom Rini wrote:
> >
> > To make testing with clang support easier, add sandbox/clang-7
> > combination to our testing matrix. To facilitate this, switch to using
> > the "sources" method that t
Hi Michal
On 10/04/2018 09:24 AM, Michal Simek wrote:
> This reverts commit c35a7d375ec8f0a8ee343ae4868be3242172632e.
> This commit is breaking SPL on zc706.
>
> Signed-off-by: Michal Simek
> ---
>
> lib/fdtdec.c | 44 +++-
> 1 file changed, 23 insertion
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/
Hello,
For the record this the second version of the series adding the
support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them
belongs to the same family Vcore III.
We found them on various advanced switches product.
The support for Ocelot already have been submit to Linux, but not yet
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 13 +
arch/mips
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT
---
arch/mips/Kconfig | 6 +
arch/mips/Makefile| 1 +
arch/mips/mach-mscc/Kconfig
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc,luton.dtsi | 87 +
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 132 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 +++
arch/mips/dts/ocelot_pcb120.dts | 12 +++
ar
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like y
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
d
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver,
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:17, Gregory CLEMENT wrote:
>> On some platforms, as the Ocelot ones, when wanting to control the CS
>> through software, it is not possible to do it through the GPIO
>> controller. Indeed, this signal is managed t
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possib
Hi Marek,
On Tue, Oct 9, 2018 at 8:26 PM Marek Vasut wrote:
>
> Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
This statement sounds like
the current code is passing the pointer address only partially.
Is it right?
> so we don't have to apply casts throughout the code.
I
Includes changes in u-boot framework to support TF-A for NXP Chassis 2
platforms. A new defconfig is added namely ls*_tfa_defconfig which will
be used for all boot sources when TF-A is used.
From: York Sun
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +
.../arm/include/asm/arch-fsl-la
Define env_ptr as static in flash and nand env driver to
allow these to compile together.
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Merged env nand specific patches to remove compilation warning
Change in v2: None
env/flash.c | 4 ++--
env/nand.c| 6 ++
includ
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
env/sf.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 494
From: Pankit Garg
Change tlb base address from OCRAM to DDR when exception level is
less than 3.
Signed-off-by: Ruchika Gupta
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
From: York Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erra
From: York Sun
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/arm
Replaces __ilog2 function call with LOG2 macro, required to
use macros in global variables.
Also, corrects the value passed in LOG2 for some PowerPC
platforms. Minimum value that can be configured is is 64K
for IFC IP.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: No
Adds TFABOOT support config option and add generic code to enable
execution from DDR.
Signed-off-by: York Sun
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Seperated TFABOOT generic code
- Moved before dependency patches
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
arch/arm/cpu/
From: Vinitha V Pillai
Includes environment.h file in ls1012aqds.c Also, enables
pfe validation in ls1012ardb.
Signed-off-by: Vinitha V Pillai
---
Change in v3: None
Change in v2: None
board/freescale/ls1012aqds/Kconfig | 10 ++
board/freescale/ls1012aqds/ls1012aqds.c |
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803
SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat
---
Ch
From: Pankit Garg
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3:
- Merged secure boot bootcmd changes
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +
arch/
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
2 files
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