On Tue, Oct 9, 2018 at 4:49 AM Marek Vasut <ma...@denx.de> wrote:
>
> On 10/08/2018 08:26 PM, Simon Goldschmidt wrote:
> > This patch prevents disabling the FPGA bridges when
> > SPL or U-Boot is executed from FPGA onchip RAM.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
> > ---
> >
> > Changes in v2:
> > - use less ifdefs and more C code for address checks
> > (but this gives a checkpatch warning because of comparing two
> > upper case constants)
> > - changed comments
> >
> > This patch depends on:
> > - CONFIG_SPL_TEXT_BASE needs to be set to 0xC0000000
> > ideally this is done by moving SPL_TEXT_BASE to Kconfig:
> > https://patchwork.ozlabs.org/patch/976918/
> > ---
> > arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 +
> > arch/arm/mach-socfpga/misc_gen5.c | 13 ++++++++++++-
> > arch/arm/mach-socfpga/spl_gen5.c | 10 +++++++---
> > 3 files changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > index bb9e3faa29..2725e9fcc3 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > @@ -6,6 +6,7 @@
> > #ifndef _SOCFPGA_BASE_ADDRS_H_
> > #define _SOCFPGA_BASE_ADDRS_H_
> >
> > +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
> > #define SOCFPGA_STM_ADDRESS 0xfc000000
> > #define SOCFPGA_DAP_ADDRESS 0xff000000
> > #define SOCFPGA_EMAC0_ADDRESS 0xff700000
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> > b/arch/arm/mach-socfpga/misc_gen5.c
> > index 429c3d6cd5..b35636b590 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void)
> >
> > void socfpga_sdram_remap_zero(void)
> > {
> > + u32 remap;
> > +
> > socfpga_nic301_slave_ns();
> >
> > /*
> > @@ -187,7 +189,16 @@ void socfpga_sdram_remap_zero(void)
> > setbits_le32(&scu_regs->sacr, 0xfff);
> >
> > /* Configure the L2 controller to make SDRAM start at 0 */
> > - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
> > + remap = 0x1; /* remap.mpuzero */
> > + if (CONFIG_SYS_TEXT_BASE >= SOCFPGA_FPGA_SLAVES_ADDRESS &&
> > + CONFIG_SYS_TEXT_BASE < SOCFPGA_STM_ADDRESS)
>
> We can detect where we're executing from at runtime, right ?
Sure, we can either read the 'pc' reg (are there predefined functions for this
in the U-Boot sources?) or take the address of this function. Which one do
you prefer?
Simon
> > + remap |= 0x8; /* remap.hps2fpga: keep fpga bridge enabled */
> > +#ifdef CONFIG_SPL_BUILD
> > + if (CONFIG_SPL_TEXT_BASE == SOCFPGA_FPGA_SLAVES_ADDRESS)
> > + remap |= 0x8; /* remap.hps2fpga: keep fpga bridge enabled */
> > +#endif
> > + writel(remap, &nic301_regs->remap);
> > +
> > writel(0x1, &pl310->pl310_addr_filter_start);
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> > b/arch/arm/mach-socfpga/spl_gen5.c
> > index be318cc0d9..5c3995be13 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -92,8 +92,11 @@ void board_init_f(ulong dummy)
> >
> > /* Put everything into reset but L4WD0. */
> > socfpga_per_reset_all();
> > - /* Put FPGA bridges into reset too. */
> > - socfpga_bridges_reset(1);
> > +
> > + if (CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS) {
> > + /* Put FPGA bridges into reset (unless booting from FPGA). */
> > + socfpga_bridges_reset(1);
> > + }
> >
> > socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > @@ -163,5 +166,6 @@ void board_init_f(ulong dummy)
> > hang();
> > }
> >
> > - socfpga_bridges_reset(1);
> > + if (CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS)
> > + socfpga_bridges_reset(1);
> > }
> >
>
>
> --
> Best regards,
> Marek Vasut
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
