set the mmc specific addresss and range as power on
write protection, and can't earse and write this range
if you enable it after mmc power on.
Signed-off-by: Lin Huang
---
drivers/mmc/mmc.c | 89 +++
include/mmc.h | 10 ++-
2 files cha
Hi Tom,
2015-12-01 21:50 GMT+01:00 Tom Rini :
> In order to fit into image constraints again, remove this feature.
>
> Signed-off-by: Tom Rini
> ---
> configs/iocon_defconfig |1 +
> include/configs/iocon.h |2 --
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/configs
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> Most driver model PCI functions have a dm_ prefix. At some point, when the
> old code is converted to driver model and the old functions are removed, we
> will drop that prefix.
>
> For consistency, we should use the dm_ prefix for all driver m
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> Most driver model PCI functions have a dm_ prefix. At some point, when the
> old code is converted to driver model and the old functions are removed, we
> will drop that prefix.
>
> For consistency, we should use the dm_ prefix for all driver m
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> At present we are using legacy functions even in the auto-configuration code
> used by driver model. Add a new pci_auto.c version which uses the correct
> API.
>
> Create a new pci_internal.h header to hold functions that are used within
> the
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> Add a function which scans the driver model device information rather
> than scanning the PCI bus again.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2: None
>
Tested-by: Bin Meng
On Wed, Dec 02, 2015 at 10:59:11AM -0700, Simon Glass wrote:
> Since commit 4188ba3 we get the following warning on rockchip boards:
>
> common/spl/spl_mmc.c:31:24: warning: ‘mmc’ may be used uninitialized in this
> function [-Wmaybe-uninitialized]
> count = mmc->block_dev.block_read(0, sector,
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
Changes in v3:
- Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options
simila
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> Adjust the SCSI command to use driver model for its PCI interface.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Use dm_pci_get_bdf()
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
___
On Mon, Nov 30, 2015 at 4:17 AM, Simon Glass wrote:
> Add a function which scans the driver model device information rather
> than scanning the PCI bus again.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2: None
>
Tested-by: Bin Meng
Hi, York,
> On Wednesday 25 November 2015 02:20:53, Huan Wang wrote:
> > [Alison Wang] I didn't meet any issue when using sf commands to write
> > and read the serial flash.
> >
> > Hi, Alexander,
> >
> > Could you show me the detail commands and process when you meet
> such
> > issue? Then I
Hi Simon,
I re-phrase all the question from previous thread and continue in this
for more discussion on spi-nor development.
> Is it intended that SPI flash should be a driver for the MTD uclass?
> Others would be NAND and CFI. From what I can tell MTD has the same
> operations as SPI flash (e
Hi Simon,
On 1 December 2015 at 04:47, Simon Glass wrote:
> Hi Jagan,
>
> On 27 November 2015 at 02:21, Jagan Teki wrote:
>> Hi Bin,
>>
>> On 27 November 2015 at 07:55, Bin Meng wrote:
>>> Hi Jagan,
>>>
>>> On Fri, Nov 27, 2015 at 2:54 AM, Jagan Teki wrote:
Hi Simon,
Some how I'
Hi Bin,
On 1 December 2015 at 15:37, Bin Meng wrote:
> The #ifdef #endif in drivers/mtd/spi/Makefile actually does nothing
> but causes confusion. Remove it.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/mtd/spi/Makefile | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/
Hi Jagan,
On Thu, Dec 3, 2015 at 6:17 PM, Jagan Teki wrote:
> Hi Bin,
>
> On 1 December 2015 at 15:37, Bin Meng wrote:
>> The #ifdef #endif in drivers/mtd/spi/Makefile actually does nothing
>> but causes confusion. Remove it.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> drivers/mtd/spi/Makefile
On Thu, Nov 26, 2015 at 8:03 PM, Jagan Teki wrote:
> This patch removes unneeded ifdef and fixed accordingly.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/mtd/spi/Makefile | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Ma
Hi Bin,
On 3 December 2015 at 10:14, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> +Jagan
>>
>> Hi Bin,
>>
>> On 1 December 2015 at 18:41, Bin Meng wrote:
>>>
>>> Hi Simon,
>>>
>>> On Wed, Dec 2, 2015 at 12:32 AM, Simon Glass wrote:
>>> > Hi Bin,
>>> >
>
Kconfig description is the same for both. Extend SPL one to indicate
that this option is for SPL only.
Signed-off-by: Michal Simek
---
drivers/core/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 15681df6d379..b68a26f
On 03.12.2015 12:12, Michal Simek wrote:
Kconfig description is the same for both. Extend SPL one to indicate
that this option is for SPL only.
Signed-off-by: Michal Simek
---
drivers/core/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/Kconfig b/dri
Hi Simon,
On 02.12.2015 18:45, Simon Glass wrote:
> Hi Stefan,
>
> On 2 December 2015 at 10:43, Stefan Roese wrote:
>> Hi Simon,
>>
>> ( Last mail for tonight - a glass of quite nice red wine is
>> waiting for me ... ;) )
>>
>
> That's the only sad thing about me being so many hours behind. Sti
On 1 December 2015 at 09:41, Simon Glass wrote:
> At present this SPI driver works by searching the PCI buses for its
> peripheral. It also uses the legacy PCI API.
>
> In addition the driver has code to determine the type of Intel PCH that is
> used (version 7 or version 9). Now that we have prop
On 30 November 2015 at 15:31, Stefano Babic wrote:
> On 30/11/2015 10:45, Peng Fan wrote:
>> Support qspi flashes for mx7dsabresd
>> 1. introduce pin mux settings
>> 2. enable qspi clock
>> 3. introduce related macro definitions
>>
>> Default QSPI is not enabled, since we need hardware rework to u
On 27 November 2015 at 15:56, Stefan Roese wrote:
> This patch enables the DM support for the SPI driver and the
> SPI NOR flash chips. Some MVEBU boards boot from SPI NOR, so
> adding the aliases and enabling CONFIG_DM_SEQ_ALIAS is needed
> here.
>
> Signed-off-by: Stefan Roese
> Cc: Luka Perkov
On 23 November 2015 at 17:43, Vignesh R wrote:
> ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
> memory-mapped read. This restricts maximum addressable flash size to
> 16MB.
> Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
> read to allow access to ad
On Thu, Dec 03, 2015 at 09:40:46AM +0100, Dirk Eibach wrote:
> Hi Tom,
>
> 2015-12-01 21:50 GMT+01:00 Tom Rini :
> > In order to fit into image constraints again, remove this feature.
> >
> > Signed-off-by: Tom Rini
> > ---
> > configs/iocon_defconfig |1 +
> > include/configs/iocon.h |2
On 12/03/2015 05:25 PM, Jagan Teki wrote:
> On 23 November 2015 at 17:43, Vignesh R wrote:
>> ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
>> memory-mapped read. This restricts maximum addressable flash size to
>> 16MB.
>> Enable the 4-byte addressing(and use 4-byte opco
On Thursday 03 December 2015 05:51 PM, Vignesh R wrote:
On 12/03/2015 05:25 PM, Jagan Teki wrote:
On 23 November 2015 at 17:43, Vignesh R wrote:
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
En
Hello Tom,
Please pull from u-boot-sparc master:
The following changes since commit be30dfbabbee12770221f434d2aa08627e712b97:
iocon: Disable FIT_VERBOSE (2015-12-01 15:49:42 -0500)
are available in the git repository at:
http://git.denx.de/u-boot-sparc.git master
for you to fetch changes
On 3.12.2015 12:22, Stefan Roese wrote:
> On 03.12.2015 12:12, Michal Simek wrote:
>> Kconfig description is the same for both. Extend SPL one to indicate
>> that this option is for SPL only.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> drivers/core/Kconfig | 2 +-
>> 1 file changed, 1 insert
Hi Jagan,
On Thu, Dec 3, 2015 at 6:24 PM, Jagan Teki wrote:
> Hi Bin,
>
> On 3 December 2015 at 10:14, Bin Meng wrote:
>> Hi Simon,
>>
>> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>>> +Jagan
>>>
>>> Hi Bin,
>>>
>>> On 1 December 2015 at 18:41, Bin Meng wrote:
Hi Simon,
Hi Stefan, Simon,
On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
> On 29 September 2015 at 23:00, Stefan Roese wrote:
>> The current "simple" address translation simple_bus_translate() is not
>> working on some platforms (e.g. MVEBU). As here more complex "ranges"
>> properties are used in
Hi Bin,
On 03.12.2015 14:34, Bin Meng wrote:
Hi Stefan, Simon,
On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
On 29 September 2015 at 23:00, Stefan Roese wrote:
The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more c
From: Siva Durga Prasad Paladugu
Don't relocate fdt in case of CONFIG_OF EMBED as the fdt is
already embedded with u-boot image.
Update fdt_blob after relocation as the fdt will be copied
during u-boot relocation.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
Reviewed-b
CONFIG_API is causing compilation error when DM_ETH is enabled because
eth_get_dev() is not available.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
include/configs/zynq-common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/zynq-common.h b/includ
Move PHYLIB from board config to defconfig
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
configs/zynq_microzed_defconfig| 1 +
configs/zynq_picozed_defconfig | 1 +
configs/zynq_zc702_defconfig | 1 +
configs/zynq_zc706_defconfig | 1 +
configs/zyn
Next step to move driver to driver model. Do not use eth_device
structure. Use private structure instead.
Add iobase to private structure to store gem iobase.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 32 +++-
1
Add return value for phy detection algorithm to stop init function when
phy is not found.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/
Check return value.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 86bb75905071..d5540ec2155c 100644
--- a/drivers/net/zynq_gem.c
+++ b/dr
This function was used for OF init before DM.
Remove this function as the part of move to DM.
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 42 --
include/netdev.h | 1 -
Move phy init code out of zynq_gem_init. DM drivers are normally calling
this code from probe function.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 47 ++-
1 file changed, 30 insertions(+), 17 dele
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
configs/xilinx_zynqmp_ep_defconfig | 1 +
configs/zynq_microzed_defconfig| 1 +
configs/zynq_picozed_defconfig | 1 +
configs/zynq_zc702_defconfig | 1 +
configs/zynq_zc706_defconfig | 1 +
configs/zynq_
Do not set interface via configs. Read information from DT.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
i
Resort code to use priv->phydev variable directly.
It will simplify move to DM.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/
Sync it with write function.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a569c77aeb60..4e93707c7ab1 100644
--- a/driv
Pass regs instead of dev because this will be chagned by
driver model.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
based on DM requirement
- Do not enable EMIO DT support by default
Signed-off-by: Michal Simek
---
Changes in v3:
- Add remove function reported by Bi
Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/net/zynq_gem.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/zyn
Hi,
On Thursday 03 December 2015 09:49:40, Huan Wang wrote:
> [Alison Wang] I could not reproduce the issue. Maybe I don't have the
> external watchdog which will reset after ~1.5s as Alexander mentioned.
Could you try to set the internal watchdog to 1s timeout? This should be more
or less the s
Hi Mugunthan,
On 23 November 2015 at 18:42, Jagan Teki wrote:
> On 23 November 2015 at 16:59, Mugunthan V N wrote:
>> On Friday 20 November 2015 05:57 PM, Jagan Teki wrote:
>>> On 20 November 2015 at 11:31, Mugunthan V N wrote:
Jagan
On Thursday 19 November 2015 03:40 PM, Jagan T
On 12/03/2015 01:49 AM, Wang Huan-B18965 wrote:
>>
>> The actual command which results in a watchdog reset is 'sf read
>> 0x8104 0x20 0x40'. Please note that this uses an external
>> watchdog which is enabled by default and resets after ~1.5s. The command
>> itself takes about 2s (
On 19 November 2015 at 12:35, Mugunthan V N wrote:
> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
>
> Signed-off-by: Mugunthan V N
> Reviewed-by: S
On 3 December 2015 at 20:17, Michal Simek wrote:
> CONFIG_API is causing compilation error when DM_ETH is enabled because
> eth_get_dev() is not available.
Then how come, freebsd elf generate w/o CONFIG_API?
>
> Signed-off-by: Michal Simek
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>
On 3 December 2015 at 20:17, Michal Simek wrote:
> Move PHYLIB from board config to defconfig
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/l
On Thu, 2015-12-03 at 01:10 +0100, Marek Vasut wrote:
> On Thursday, November 12, 2015 at 03:33:42 AM, Chin Liang See wrote:
> > On Thu, 2015-11-12 at 01:53 +0100, Marek Vasut wrote:
> > > On Thursday, November 12, 2015 at 01:49:09 AM, Chin Liang See
> > > wrote:
> > > > Hi Marek,
> > > >
> > > >
On 3 December 2015 at 20:18, Michal Simek wrote:
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Michal
On 3 December 2015 at 20:18, Michal Simek wrote:
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
>
> Changes in v3: None
> Changes in v2: None
>
> configs/xilinx_zynqmp_ep_defconfig | 1 +
> configs/zynq_microzed_defconfig| 1 +
> configs/zynq_picozed_defconfig | 1 +
> co
On 3 December 2015 at 20:18, Michal Simek wrote:
> Do not set interface via configs. Read information from DT.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.
On Thursday, December 03, 2015 at 05:11:23 PM, Chin Liang See wrote:
[...]
> > I have another board where I cannot use UBI on QSPI NOR and reverting
> > this
> > patch magically fixes things.
>
> I was testing this too as enabling the UBIFS on NOR and here are my
> output. Wonder how to simulate
On 3 December 2015 at 20:17, Michal Simek wrote:
> This function was used for OF init before DM.
> Remove this function as the part of move to DM.
>
> Signed-off-by: Michal Simek
> Reviewed-by: Simon Glass
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
__
On 3 December 2015 at 20:17, Michal Simek wrote:
> Add return value for phy detection algorithm to stop init function when
> phy is not found.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
U-Boot mailing list
U-
On 3 December 2015 at 20:17, Michal Simek wrote:
> Sync it with write function.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
U-Boot mailing list
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On 3 December 2015 at 20:17, Michal Simek wrote:
> Check return value.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
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On 12/01/2015 07:27 PM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Freescale ARM-based Layerscape contains a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> ls
Hi Simon,
On 26 November 2015 at 23:20, Simon Glass wrote:
> Hi Jagan,
>
> On 26 November 2015 at 04:03, Jagan Teki wrote:
>> flash operations are defined as static and reuse them
>> with function-pointers so call them with generic
>> function pounters instead of calling like normal functions.
>
On 12/03/2015 07:12 AM, Stefan Roese wrote:
Hi Bin,
On 03.12.2015 14:34, Bin Meng wrote:
Hi Stefan, Simon,
On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
On 29 September 2015 at 23:00, Stefan Roese wrote:
The current "simple" address translation simple_bus_translate() is not
working o
From: Olliver Schinagl
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to enable the clocks for these 2 i2c busses.
This patch enables the clocks for i2c bus 4 and 5 on sun7i.
Signed-off-by: Olliver Schinagl
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 4
From: Olliver Schinagl
Paul enabled all I2C ports for sunxi but forgot the clock on twi 4 and 5 for
sun7i.
And a small non code changing whitespace fix
Tested on Olimex Lime2
Olliver Schinagl (2):
sunxi: twi: enable clocks on sun7i
sun4i: clock: cleanup some whitespace errors
arch/arm/c
From: Olliver Schinagl
Add some spaces around operators.
Signed-off-by: Olliver Schinagl
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index e
On 12/02/2015 04:15 PM, Stefan Brüns wrote:
pxe get derives the pxelinux config file name from the bootfile name,
but the bootfile itself is never used and might not even exist.
Disable bootfile autoload to avoid the delay.
I wasn't CC'd on this and only accidentally noticed it, since it just
spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
drivers/spi/spi-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
inde
Hi Stefan,
On 3 December 2015 at 04:31, Stefan Roese wrote:
>
> Hi Simon,
>
> On 02.12.2015 18:45, Simon Glass wrote:
> > Hi Stefan,
> >
> > On 2 December 2015 at 10:43, Stefan Roese wrote:
> >> Hi Simon,
> >>
> >> ( Last mail for tonight - a glass of quite nice red wine is
> >> waiting for me .
SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.
Cc: Mugunthan V N
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
drivers/spi/ti_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/ti_qspi.c b/driver
Hi,
On 03-12-15 17:09, Jagan Teki wrote:
On 3 December 2015 at 20:17, Michal Simek wrote:
CONFIG_API is causing compilation error when DM_ETH is enabled because
eth_get_dev() is not available.
Then how come, freebsd elf generate w/o CONFIG_API?
Signed-off-by: Michal Simek
---
Changes in v
Hi!
> > > OK, this is bad. Originally, if we didn't specify these in the DT, we
> > > would
> > > use the default values of 0x3 and 0x0 , but now we do the
> > > calibration. I wonder,
> > > do we care about DT ABI compatibility on the U-Boot level or not ?
> >
> > If the compatibility failed, it
On Tue 2015-12-01 10:48:31, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Add system manager defines for Arria10.
>
> Signed-off-by: Dinh Nguyen
With whitespace cleaned up:
Acked-by: Pavel Machek
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http:/
On Tue 2015-12-01 19:51:39, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 05:48:32 PM, dingu...@opensource.altera.com
> wrote:
> > From: Dinh Nguyen
> >
> > Add the defines for the reset manager and some basic reset functionality.
> >
> > Signed-off-by: Dinh Nguyen
> > ---
> > v2: inte
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > + puts("CPU : Altera SOCFPGA Arria 10 Platform\n");
>
> No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> platform",
> CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?
>
Well. .. cpu is "gener
On Tue 2015-12-01 17:33:02, Dinh Nguyen wrote:
> On 12/01/2015 05:30 PM, Marek Vasut wrote:
> > On Wednesday, December 02, 2015 at 12:20:47 AM,
> > dingu...@opensource.altera.com
> > wrote:
> >> From: Dinh Nguyen
> >>
> >> Not sure what made this macro questionable, but edit the macro to be
> >>
On Wed 2015-12-02 13:31:27, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Add the defines for the reset manager and some basic reset functionality.
>
> Signed-off-by: Dinh Nguyen
> ---
> v4: rename mod_reset names to be used by both gen5 and a10
> v3: remove duplicate reset func
Hi Bin,
On 2 December 2015 at 22:11, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:58, Bin Meng wrote:
>>> There is no need to pass shared_data to fsp_continue() so we can
>>> remove unnecessary codes that simplifies
Hi Bin,
On 2 December 2015 at 21:57, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Nov 26, 2015 at 12:52 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 19 November 2015 at 20:38, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Fri, Nov 20, 2015 at 11:09 AM, Simon Glass wrote:
Hi,
I'm wondering w
Hi Bin,
On 2 December 2015 at 22:18, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:59, Bin Meng wrote:
>>> FSP has several config data like UPD, HDA verb table which can be
>>> overridden or provided by bootloader. C
Hi Michal,
On 2 December 2015 at 22:00, Bin Meng wrote:
> Hi Michal,
>
> On Wed, Dec 2, 2015 at 9:51 PM, Michal Simek wrote:
>> On 2.12.2015 14:16, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Wed, Dec 2, 2015 at 7:36 PM, Michal Simek
>>> wrote:
>>
>> ...
>>
+
+ offset = fdtdec_lo
Hi Bin,
On 2 December 2015 at 22:22, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:59, Bin Meng wrote:
>>> Since VPD/UPD may not exist on every FSP, move the codes that
>>> verifies VPD/UPD to chipset-specific update
Hi,
On 3 December 2015 at 06:27, Bin Meng wrote:
> Hi Jagan,
>
> On Thu, Dec 3, 2015 at 6:24 PM, Jagan Teki wrote:
>> Hi Bin,
>>
>> On 3 December 2015 at 10:14, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
+Jagan
Hi Bin,
On 1
On 3 December 2015 at 10:12, Jagan Teki wrote:
> spi-3wire is used when SI/SO signals shared so get
> the same from dts node and assign to mode on slave
> plat->mode.
>
> Cc: Simon Glass
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/spi-uclass.c | 2 ++
> 1 file changed, 2 insertions(+)
Acke
On 3 December 2015 at 07:48, Michal Simek wrote:
>
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Micha
On 3 December 2015 at 10:12, Jagan Teki wrote:
> SPI_3WIRE is spi mode not spi flags, so this patch fixed
> the spi-3wire checking throgh mode instead of flags.
>
> Cc: Mugunthan V N
> Cc: Simon Glass
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/ti_qspi.c | 2 +-
> 1 file changed, 1 inserti
Hi Simon,
On Thu, Dec 3, 2015 at 12:57 PM, Simon Glass wrote:
>
> On 3 December 2015 at 07:48, Michal Simek wrote:
> >
> > - Enable DM_ETH by default for Zynq and ZynqMP
> > - Remove board_eth_init code
> > - Change miiphy_read function to return value instead of error code
> > based on DM req
Hi Joe,
On 3 December 2015 at 12:00, Joe Hershberger wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 12:57 PM, Simon Glass wrote:
>>
>> On 3 December 2015 at 07:48, Michal Simek wrote:
>> >
>> > - Enable DM_ETH by default for Zynq and ZynqMP
>> > - Remove board_eth_init code
>> > - Change miiphy_
Hi Tom,
2015-12-03 13:19 GMT+01:00 Tom Rini :
> On Thu, Dec 03, 2015 at 09:40:46AM +0100, Dirk Eibach wrote:
>> Hi Tom,
>>
>> 2015-12-01 21:50 GMT+01:00 Tom Rini :
>> > In order to fit into image constraints again, remove this feature.
>> >
>> > Signed-off-by: Tom Rini
>> > ---
>> > configs/ioco
On 12/02/2015 08:47 PM, Marek Vasut wrote:
> On Wednesday, December 02, 2015 at 08:31:28 PM,
> dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Add arch_early_init_r function. The Arria10 has a firewall protection
>> around the SDRAM and OCRAM. These firewalls are to be disable
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v5: rename the mod_reest on A10 to match those in gen5
v4: rename mod_reset names to be used by both gen5 and a10
v3: remove duplicate reset function
use CONFIG_SOCFPGA
From: Dinh Nguyen
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/ma
On Thursday, December 03, 2015 at 07:35:54 PM, Pavel Machek wrote:
> > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > + puts("CPU : Altera SOCFPGA Arria 10 Platform\n");
> >
> > No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> > platform", CPU is still Altera SoCFPGA
On 11/22/2015 08:53 AM, Tom Rini wrote:
On Thu, Nov 19, 2015 at 09:48:11PM +0800, Thomas Chou wrote:
Unify serial_tegra, and use the generic binding.
Signed-off-by: Thomas Chou
Reviewed-by: Tom Rini
Acked-by: Simon Glass
Applied to u-boot/master, thanks!
FYI, this patch causes at least
On 11/19/2015 08:26 PM, Simon Glass wrote:
Move this option to Kconfig and fix up all users.
The version of this that got committed (as fde7e18938d8) contains merge
markers in a four files.
___
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Hi Stephen,
On 3 December 2015 at 14:33, Stephen Warren wrote:
> On 11/22/2015 08:53 AM, Tom Rini wrote:
>>
>> On Thu, Nov 19, 2015 at 09:48:11PM +0800, Thomas Chou wrote:
>>
>>> Unify serial_tegra, and use the generic binding.
>>>
>>> Signed-off-by: Thomas Chou
>>> Reviewed-by: Tom Rini
>>> Ac
Hi,
On 3 December 2015 at 14:35, Stephen Warren wrote:
> On 11/19/2015 08:26 PM, Simon Glass wrote:
>>
>> Move this option to Kconfig and fix up all users.
>
>
> The version of this that got committed (as fde7e18938d8) contains merge
> markers in a four files.
Ugh. I had that problem locally in
Hi,
On 3 December 2015 at 14:55, Nye Liu wrote:
>
> On 11/19/2015 6:15 AM, Simon Glass wrote:
>> Hi,
>>
>> On 18 November 2015 at 17:37, Nye Liu wrote:
>>> ---
>>> tools/mkimage.c | 32 +++-
>>> 1 file changed, 19 insertions(+), 13 deletions(-)
>>>
>>
>> Can you plea
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