On Thursday 03 December 2015 05:51 PM, Vignesh R wrote:
On 12/03/2015 05:25 PM, Jagan Teki wrote:
On 23 November 2015 at 17:43, Vignesh R <vigne...@ti.com> wrote:
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
read to allow access to addresses above 16MB.
What about sf side, since we don't have 4-byte opcode support yet?
Well, the sf is accessing >16MB address space using EXT_ADDR registers
via BAR support (for regular spi read/write). But, memory-mapped read
doesn't support using EXT_ADDR, hence 4-byte opcode needs to be used for
during mmap transfers to access >16MB.
So, there is no need to have 4-byte opcode support from sf side for
memory-mapped reads - true?
Signed-off-by: Ravi Babu <ravib...@ti.com>
[vigne...@ti.com: Re-word commit description]
Signed-off-by: Vignesh R <vigne...@ti.com>
---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix
flash.
drivers/spi/ti_qspi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 646dd899d3ec..0a032845866d 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -48,14 +48,14 @@
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
-#define QSPI_CMD_READ_QUAD (0x6b << 0)
+#define QSPI_CMD_READ_QUAD (0x6c << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
+#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
-#define QSPI_CMD_WRITE (0x2 << 16)
+#define QSPI_CMD_WRITE (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
/* ti qspi register set */
--
2.6.3
thanks!
--
Jagan.
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