Make the cast explicit for "warning: cast to pointer from integer of different
size".
Signed-off-by: Gong Qianyu
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 494f683..ce58c58 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -44,7 +44,7 @@ static int mmc_load_ima
Modify the data pointer type from ulong* to u32*.
For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c:
"while (*data++);" data will point to the next 64 bits each time. As the uImage
file generated by mkimage tool keeps the same data format in either 32-bit or
64-bit
pl
Hi Andrew,
On Tue, Jul 21, 2015 at 1:10 AM, Andrew Bradford
wrote:
> Hi Bin,
>
> On 07/16 18:47, Bin Meng wrote:
>> Hi Simon, Andrew,
>>
>> Just noticed that Intel has released the FSP for BayTrail version 4.
>>
>> The release notes is at here:
>> http://www.intel.com/content/www/us/en/embedded/s
Hello Simon,
On 07/30/2015 04:05 AM, Simon Glass wrote:
Hi Przemyslaw,
On 10 July 2015 at 05:53, Przemyslaw Marczak wrote:
Hello Simon,
On 07/03/2015 02:16 AM, Simon Glass wrote:
Add support for all BUCK regulators, now that the correct register is
accessed for each.
Signed-off-by: Simon
On Tue, Jul 14, 2015 at 12:52 AM, Peter Robinson wrote:
> These two patches consolidate the fuse and thermal options. They're both
> options that are standard SoC features so should be there by default for all
> devices.
What's the status of getting these pulled in?
Peter
___
On Wed, 2015-07-29 at 22:39 +0100, Peter Griffin wrote:
> HiKey is the first 96boards consumer edition compliant board. It
> features a hi6220
> SoC which has eight ARM A53 cpu's.
>
> This initial port adds support for: -
> 1) Serial
> 2) eMMC / SD card
> 3) USB
> 4) GPIO
>
> It has been tested
On Thursday, July 30, 2015 at 02:42:26 AM, Tom Rini wrote:
> On Thu, Jul 30, 2015 at 01:36:07AM +0200, Marek Vasut wrote:
> > On Wednesday, July 29, 2015 at 11:39:29 PM, Peter Griffin wrote:
> > > This patch makes the dwc2 controller like ehci / ohci / xhci
> > > controllers by calling the board_us
On Thu, Jul 30, 2015 at 9:46 AM, Sjoerd Simons
wrote:
> On Wed, 2015-07-29 at 22:39 +0100, Peter Griffin wrote:
>> HiKey is the first 96boards consumer edition compliant board. It
>> features a hi6220
>> SoC which has eight ARM A53 cpu's.
>>
>> This initial port adds support for: -
>> 1) Serial
>>
Hi Haikun, Simon,
On Fri, Jul 10, 2015 at 11:50 AM, Wang Haikun wrote:
> On 7/10/2015 6:06 AM, Simon Glass wrote:
>> Hi,
>>
>> On 9 July 2015 at 05:58, Haikun Wang wrote:
>>> Showing both:
>>> Model: Freescale Layerscape 2085a QDS Board
>>> Board: LS2085E-QDS, Board Arch: V1, Board version: B, b
This series adds Intel Bayley Bay board support, which is another
BayTrail SoC based board, like MinnowMax.
Tested booting Linux kernel 4.0, under PIC mode (kernel uses PIRQ
table U-Boot creates) and I/O APIC mode (kernel uses MP table U-Boot
creates). Verified PCIe root port interrupt swizzling w
We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.
Signed-off-by: Bin Meng
---
drivers/pci/pci_rom.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index a33efae..26db3ca 100644
--- a/d
bd->bi_dram[] has both start address and size defined as 32-bit,
which is not the case on some platforms where >=4GiB memory bank
is used. Change them to support such memory banks.
Signed-off-by: Bin Meng
---
common/board_f.c | 2 +-
include/asm-generic/u-boot.h | 4 ++--
2 files ch
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng
---
arch/x86/cpu/baytrail/valleyview.c | 8 +
arch/x86/dts/bayleybay.dts | 63 ++
configs/bayleybay_defconfig
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
b/arch/x86/includ
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng
---
board/intel/minnowmax/minnowmax.c | 12
include/configs/minnowmax.h | 2 --
2 files cha
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng
---
arch/x86/dts/Makefile | 3 +-
arch/x86/dts/bayleybay.dts| 134 ++
board/intel/Kconfig | 9 ++
2015-07-30 19:42 GMT+09:00 Bin Meng :
> Hi Haikun, Simon,
>
> On Fri, Jul 10, 2015 at 11:50 AM, Wang Haikun
> wrote:
>> On 7/10/2015 6:06 AM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 9 July 2015 at 05:58, Haikun Wang wrote:
Showing both:
Model: Freescale Layerscape 2085a QDS Board
Bo
On Wed, Jul 29, 2015 at 10:09:57AM -0600, Stephen Warren wrote:
> On 07/29/2015 05:07 AM, Thierry Reding wrote:
> >On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote:
> >>On 07/24/2015 04:01 PM, Tom Warren wrote:
> >>>Based on Venice2, incorporates Stephen Warren's
> >>>latest P2571 pin
On Thu, Jul 30, 2015 at 6:47 PM, Masahiro Yamada
wrote:
> 2015-07-30 19:42 GMT+09:00 Bin Meng :
>> Hi Haikun, Simon,
>>
>> On Fri, Jul 10, 2015 at 11:50 AM, Wang Haikun
>> wrote:
>>> On 7/10/2015 6:06 AM, Simon Glass wrote:
Hi,
On 9 July 2015 at 05:58, Haikun Wang wrote:
> Sh
Hi Simon,
On Wed, Jul 29, 2015 at 5:01 PM, Bin Meng wrote:
> Hi Simon,
>
> On Wed, Jul 29, 2015 at 9:08 AM, Bin Meng wrote:
>> Hi Simon,
>>
>> On Wed, Jul 29, 2015 at 8:48 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>> On 28 July 2015 at 18:46, Bin Meng wrote:
Hi Simon,
On Wed, Jul
Enable Secure IOU setup to enable U-Boot to run in EL3 without
setting from ATF.
Signed-off-by: Michal Simek
---
arch/arm/cpu/armv8/zynqmp/Kconfig | 4
arch/arm/include/asm/arch-zynqmp/hardware.h | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv8/zynqmp/K
Enable Secure IOU setup to enable U-Boot to run in EL3 without
setting from ATF.
Signed-off-by: Michal Simek
---
arch/arm/cpu/armv8/zynqmp/Kconfig | 4
arch/arm/include/asm/arch-zynqmp/hardware.h | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv8/zynqmp/K
Enable gem0 and setup phy addr for EP.
Signed-off-by: Michal Simek
---
This patch depends on
"armv8: caches: Added routine to set non cacheable region"
https://patchwork.ozlabs.org/patch/488800/
---
include/configs/xilinx_zynqmp_ep.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/inclu
Enable gem0 and setup phy addr for EP.
Signed-off-by: Michal Simek
---
This patch depends on
"armv8: caches: Added routine to set non cacheable region"
https://patchwork.ozlabs.org/patch/488800/
---
include/configs/xilinx_zynqmp_ep.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/inclu
2015-07-30 19:51 GMT+09:00 Bin Meng :
> On Thu, Jul 30, 2015 at 6:47 PM, Masahiro Yamada
> wrote:
>> 2015-07-30 19:42 GMT+09:00 Bin Meng :
>>> Hi Haikun, Simon,
>>>
>>> On Fri, Jul 10, 2015 at 11:50 AM, Wang Haikun
>>> wrote:
On 7/10/2015 6:06 AM, Simon Glass wrote:
> Hi,
>
> On
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Additionally, ARM64 devices typically run a secure monitor in EL3 and
> U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
> code and data. These carve-outs are located at the top of 32
Hello,
Commit d718ded056eefb6239bd2e0a57b7f6d99c6e9e4b introduced translation of UUID
binary
data to GUID string representation.
So, for example, if I use the 'gpt' command to create a partition table and
pass a
'uuid' parameter like this:
=> gpt write mmc 0
"uuid_disk=${uuid_disk};start=2MiB,n
On Tuesday, July 28, 2015 at 09:21:50 PM, Dinh Nguyen wrote:
> On 7/27/15 3:49 PM, Marek Vasut wrote:
> > The current bridge reset code, which de-asserted the bridge reset,
> > was activelly polling whether the FPGA is programmed and ready and
>
> s/activelly/actively
>
> Again...only comment for
Hi Peter,
On 30/07/2015 10:33, Peter Robinson wrote:
> On Tue, Jul 14, 2015 at 12:52 AM, Peter Robinson wrote:
>> These two patches consolidate the fuse and thermal options. They're both
>> options that are standard SoC features so should be there by default for all
>> devices.
>
> What's the st
>> On Tue, Jul 14, 2015 at 12:52 AM, Peter Robinson
>> wrote:
>>> These two patches consolidate the fuse and thermal options. They're both
>>> options that are standard SoC features so should be there by default for all
>>> devices.
>>
>> What's the status of getting these pulled in?
>>
>
> I hav
On Thursday, July 30, 2015 at 04:13:14 PM, LEMIEUX, SYLVAIN wrote:
> Hi Marek,
Hi!
> Thanks for the feedback. I will do the change and submit a new revision of
> the patch.
>
> For your question regarding reference to UART 5 inside the USB driver;
> * It is possible to also route the UART5 Tx/R
Hi Marek,
Thanks for the feedback. I will do the change and submit a new revision of the
patch.
For your question regarding reference to UART 5 inside the USB driver;
* It is possible to also route the UART5 Tx/Rx pin to the USB D+ and D- pins;
the driver ensure this is not selected.
For
Hi,
On 30 July 2015 at 04:55, Masahiro Yamada wrote:
>
> 2015-07-30 19:51 GMT+09:00 Bin Meng :
> > On Thu, Jul 30, 2015 at 6:47 PM, Masahiro Yamada
> > wrote:
> >> 2015-07-30 19:42 GMT+09:00 Bin Meng :
> >>> Hi Haikun, Simon,
> >>>
> >>> On Fri, Jul 10, 2015 at 11:50 AM, Wang Haikun
> >>> wrot
Hi Masahiro,
On 29 July 2015 at 23:16, Masahiro Yamada wrote:
> Hi Simon,
>
>
> 2015-07-30 11:06 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> On 15 July 2015 at 02:16, Masahiro Yamada
>> wrote:
>>>
>>> Now, a simple pinctrl patch is being proposed by Simon.
>>> http://patchwork.ozlabs.org/patc
Hi Simon,
On Thu, Jul 30, 2015 at 10:53 PM, Simon Glass wrote:
> Hi,
>
> On 30 July 2015 at 04:55, Masahiro Yamada
> wrote:
>>
>> 2015-07-30 19:51 GMT+09:00 Bin Meng :
>> > On Thu, Jul 30, 2015 at 6:47 PM, Masahiro Yamada
>> > wrote:
>> >> 2015-07-30 19:42 GMT+09:00 Bin Meng :
>> >>> Hi Haikun
On 07/30/2015 05:04 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
From: Stephen Warren
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These
Hi,
On 30 July 2015 at 09:43, Stephen Warren wrote:
>
> On 07/30/2015 05:04 AM, Thierry Reding wrote:
>>
>> On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> Additionally, ARM64 devices typically run a secure monitor in EL3 and
>>> U-Boot in EL2
Hi Sjoerd,
On 30 July 2015 at 09:46, Sjoerd Simons
wrote:
> On Wed, 2015-07-29 at 22:39 +0100, Peter Griffin wrote:
> > HiKey is the first 96boards consumer edition compliant board. It
> > features a hi6220
> > SoC which has eight ARM A53 cpu's.
> >
> > This initial port adds support for: -
> >
Hi Albert / Tom,
This series adds support for the first 96boards consumer edition HiKey board.
More information can be found about this board at the following link
https://www.96boards.org/products/hikey/.
This initial port adds support for: -
1) Serial
2) eMMC and sd card
3) USB
4) GPIO
It has
This patch makes the dwc2 controller like ehci / ohci / xhci controllers
by calling the board_usb_init() function from usb_lowlevel_init.
This can then be implemented by specific platforms to initialise
their USB hardware (phys / clocks etc).
Signed-off-by: Peter Griffin
---
drivers/usb/host/dw
This patch adds support for the GPIO perif found on hi6220
SoC.
Signed-off-by: Peter Griffin
---
arch/arm/include/asm/arch-hi6220/gpio.h | 29 ++
drivers/gpio/Makefile | 2 +
drivers/gpio/hi6220_gpio.c | 95 +
3 files change
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.
Signed-off-by: Peter Griffin
Reviewed-by: Simon Glass
---
arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 +
drivers/mmc/Makefile
HiKey is the first 96boards consumer edition compliant board. It features a
hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
1) Serial
2) eMMC / SD card
3) USB
4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33
executable.
Notes:
eMM
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin
---
arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++
.../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 +
This adds a simple pmic driver for the hi6553 pmic which is used in
conjunction with the hi6220 SoC on the hikey board. Eventually this
driver will be updated to be a proper UCLASS PMIC driver which
can parse the voltages direct from device tree.
Signed-off-by: Peter Griffin
---
drivers/power/pm
To help others with compiling and flashing ATF and u-boot add
a README for this board.
Signed-off-by: Peter Griffin
---
board/hisilicon/hikey/README | 160 +++
1 file changed, 160 insertions(+)
create mode 100644 board/hisilicon/hikey/README
diff --git a
This patch adds basic pinmux support for the hi6220 SoC,
which is found on the hikey board.
Signed-off-by: Peter Griffin
---
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/hisilicon/Makefile | 9 ++
arch/arm/cpu/armv8/hisilicon/pinmux.c | 184
Signed-off-by: Peter Griffin
---
hikey-u-boot.mak | 33 +
1 file changed, 33 insertions(+)
create mode 100644 hikey-u-boot.mak
diff --git a/hikey-u-boot.mak b/hikey-u-boot.mak
new file mode 100644
index 000..f4cd547
--- /dev/null
+++ b/hikey-u-boot.mak
@@ -0,
(It'd be nice if all the irrelevant context could be trimmed so it was
possible to quickly find the responses within the patch. As it is, there
are about 5 lines of response in hundreds of lines of quoted patch,
which makes it very easy to miss things and wastes time).
On 07/29/2015 08:42 PM,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Thursday, July 30, 2015 11:03 AM
> To: Tom Warren; Simon Glass
> Cc: U-Boot Mailing List; Stephen Warren; Thierry Reding
> Subject: Re: [PATCH 1/2] ARM: tegra: Add e2220-1170 board
>
> (It'd be nice if all t
On 07/29/2015 05:02 PM, Simon Glass wrote:
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren wrote:
Commit message?
I guess I can add one, but there really much useful additional
information I can give.
I've also been "guilty" of pushing for commit messages for cases like
this, but
Hi Tom.
On 29 July 2015 at 20:42, Tom Warren wrote:
> Simon,
>
> I can respond to your Kconfig questions below.
>
>> -Original Message-
>> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
>> Sent: Wednesday, July 29, 2015 4:02 PM
>> To: Stephen Warren
>> Cc: U-Boot
Hi Stephen,
On 30 July 2015 at 12:13, Stephen Warren wrote:
> On 07/29/2015 05:02 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 29 July 2015 at 13:48, Stephen Warren wrote:
>>>
>>>
>>
>> Commit message?
>
>
> I guess I can add one, but there really much useful additional information I
> can
On 07/29/2015 02:13 PM, Tom Warren wrote:
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected
On 07/30/2015 05:19 AM, Palacios, Hector wrote:
Hello,
Commit d718ded056eefb6239bd2e0a57b7f6d99c6e9e4b introduced translation of UUID
binary
data to GUID string representation.
So, for example, if I use the 'gpt' command to create a partition table and
pass a
'uuid' parameter like this:
=> gp
On 07/30/2015 09:52 AM, Simon Glass wrote:
Hi,
On 30 July 2015 at 09:43, Stephen Warren wrote:
On 07/30/2015 05:04 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
From: Stephen Warren
Additionally, ARM64 devices typically run a secure monitor in
Hi Stephen,
On 30 July 2015 at 12:47, Stephen Warren wrote:
> On 07/30/2015 09:52 AM, Simon Glass wrote:
>>
>> Hi,
>>
>> On 30 July 2015 at 09:43, Stephen Warren wrote:
>>>
>>>
>>> On 07/30/2015 05:04 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warr
This little series updates the e1000 Ethernet driver to support driver
model. It also moves the configuration to Kconfig and adjusts all boards
using Masahiro's excellent moveconfig tool.
Simon Glass (6):
dm: core: Add a way to set a device name
dm: core: Fix a typo in the uclass_get_device_b
We cannot currently include any header files in the C files since common.h
needs to be included first, and it is in the header file. Move it.
Signed-off-by: Simon Glass
---
drivers/net/e1000.c | 1 +
drivers/net/e1000.h | 1 -
drivers/net/e1000_spi.c | 1 +
3 files changed, 2 insertions
Some devices are bound entirely by probing and do not have the benefit of
a device tree to give them a name. This is very common with PCI and USB. In
most cases this is fine, but we should add an official way to set a device
name. This should be called in the device's bind() method.
Signed-off-by:
This function comment has a typo. Fix it.
Signed-off-by: Simon Glass
---
include/dm/uclass.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 3fe1739..d56877c 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -130,7
Update this driver to support driver model.
Signed-off-by: Simon Glass
---
drivers/net/e1000.c | 137
drivers/net/e1000.h | 4 ++
2 files changed, 141 insertions(+)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 3a1d2ad..3db0
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.
Also refactor the code so that code that the driver model implementation
will share are available in functions
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass
---
README | 19 --
configs/CSQ_CS908_defconfig | 2 +-
configs/Mele_A1000G_quad_defconfig | 2 +-
configs/Mini-X_defconfig
On 07/30/2015 01:00 PM, Simon Glass wrote:
Hi Stephen,
On 30 July 2015 at 12:47, Stephen Warren wrote:
...
At least initially, we're targeting booting the system with the same
bootloader that L4T and Android use for unification. U-Boot runs after the
base security/... environment is set up to
Commit 488d19c (patman: add distutils based installer) has the side effect
of making patman run twice with each invocation. Fix this by checking for
'main program' invocation in patman.py. This is good practice in any case.
Signed-off-by: Simon Glass
---
tools/patman/patman.py | 5 -
1 file
On 30 July 2015 at 04:49, Bin Meng wrote:
> We should not set up kernel screen_info when the vesa parameters are
> insane, otherwise kernel will panic.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pci/pci_rom.c | 4
> 1 file changed, 4 insertions(+)
Acked-by: Simon Glass
On 30 July 2015 at 04:49, Bin Meng wrote:
> Intel Bayley Bay board is a BayTrail based board. Add this board
> with existing baytrail fsp support.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/dts/Makefile | 3 +-
> arch/x86/dts/bayleybay.dts| 134
> ++
Hi Bin,
On 30 July 2015 at 04:49, Bin Meng wrote:
> bd->bi_dram[] has both start address and size defined as 32-bit,
> which is not the case on some platforms where >=4GiB memory bank
> is used. Change them to support such memory banks.
>
> Signed-off-by: Bin Meng
> ---
>
> common/board_f.c
On 30 July 2015 at 04:49, Bin Meng wrote:
> BayTrail FSP Gold4 release adds one UPD parameter to control IGD
> enable/disable.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Acked-by: Simon Glass
On 30 July 2015 at 04:49, Bin Meng wrote:
> This commit adds the microcode blob for BayTrail-I B0 stepping,
> CPUID signature 30671h.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/dts/microcode/m0230671117.dtsi | 4244
> +++
> 1 file changed, 4244 insertions(+)
> c
Hi Bin,
On 30 July 2015 at 04:49, Bin Meng wrote:
> Add PCI IRQ routing information in the board device tree and enable
> writing PIRQ routing table and MP table.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/x86/cpu/baytrail/valleyview.c | 8 +
> arch/x86/dts/bayleybay.dts | 63
>
On 30 July 2015 at 04:49, Bin Meng wrote:
> On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
> into the SoC which is enabled by the FSP. Remove the smsc47x superio
> initialization codes.
>
> Signed-off-by: Bin Meng
> ---
>
> board/intel/minnowmax/minnowmax.c | 12 ---
On Tue, Jul 28, 2015 at 10:19 AM, Ash Charles wrote:
> I suspect testing u-boot v2015.07 on another OMAP35xx platform besides
> Overo will be most useful to confirm the scope of the problem. Anyone
> have a board and willing to test? I'm happy to send binaries :).
Hi,
FWIW, I just tried this wit
On 07/30/2015 12:23 PM, Simon Glass wrote:
Hi Stephen,
On 30 July 2015 at 12:13, Stephen Warren wrote:
On 07/29/2015 05:02 PM, Simon Glass wrote:
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren wrote:
diff --git a/board/nvidia/e2220-1170/e2220-1170.c
b/board/nvidia/e2220-1170/e2220
Pleas ignore this last patch. I didn't mean to send it as part of the v4
series.
regards,
Peter.
On 30 July 2015 at 18:55, Peter Griffin wrote:
> Signed-off-by: Peter Griffin
> ---
> hikey-u-boot.mak | 33 +
> 1 file changed, 33 insertions(+)
> create mode 10
From: Stephen Warren
Add a comment block to the top of each generated Tegra pinmux header file
indicating that the file was auto-generated, should not be manually
edited, and with a pointer to the tool and command used to generate it.
Signed-off-by: Stephen Warren
---
board/nvidia/jetson-tk1/p
AM43XX SoCs support up to 192 GPIO signals.
Make this amount available to the driver.
Cc: Albert Aribaud
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
arch/arm/include/asm/arch-am33xx/gpio.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h
This series adds initial support for CM-T43, an AM437x based SoM.
This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM
detection.
Cc: Igor Grinberg
Cc: Albert Aribaud
Cc: Pantelis Antoniou
Cc: Jagan Teki
Cc: Tom Rini
Nikita Kiryanov (6):
spi: omap3_spi: add am43xx suppo
Enable 8bit interface on HSMMC2 for am43xx to support 8bit eMMC chips.
Cc: Pantelis Antoniou
Cc: Igor Grinberg
Cc: Albert Aribaud
Signed-off-by: Nikita Kiryanov
---
drivers/mmc/omap_hsmmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/omap_hsmmc.c b/driv
Add support for AM43XX to the omap3_spi driver.
Cc: Jagan Teki
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
drivers/spi/omap3_spi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index ab7cd84..4af22c1 100644
--- a/
The CMD(DAT) lines reset procedure described in the OMAP4(AM335x,
OMAP5, DRA7xx) TRMs is also necessary for AM43XX. Enable it in the
driver.
Cc: Pantelis Antoniou
Cc: Igor Grinberg
Cc: Albert Aribaud
Signed-off-by: Nikita Kiryanov
---
drivers/mmc/omap_hsmmc.c | 2 +-
1 file changed, 1 inserti
Add spi clock to the list of am43xx basic clocks to make the SPI
subsystem available on am43xx systems.
Cc: Albert Aribaud
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/am33xx
Add initial support for CM-T43, an AM437x based SoM.
This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM
detection.
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
arch/arm/Kconfig | 6 +
board/compulab/cm_t43/Kconfi
All T114+ Tegra boards should be using the Kconfig
TEGRA114_SPI switch. Remove it from include/config
and put it into defconfig. Also removed unused
TEGRA114_SPI_CTRLS from T114+ configs.
All Tegra SoCs build OK with this change.
Signed-off-by: Tom Warren
---
configs/dalmore_defconfig| 1 +
Removed NS16550_COM1 #define, not used since there's no SPL for T210
Also changed the number of USB controllers to 1 as only USBD is used.
Signed-off-by: Tom Warren
---
include/configs/p2571.h | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/include/configs/p2571.h b/inc
On 07/30/2015 03:09 PM, Tom Warren wrote:
Removed NS16550_COM1 #define, not used since there's no SPL for T210
Also changed the number of USB controllers to 1 as only USBD is used.
Acked-by: Stephen Warren
___
U-Boot mailing list
U-Boot@lists.denx.de
On 07/30/2015 02:57 PM, Tom Warren wrote:
All T114+ Tegra boards should be using the Kconfig
TEGRA114_SPI switch. Remove it from include/config
and put it into defconfig. Also removed unused
TEGRA114_SPI_CTRLS from T114+ configs.
All Tegra SoCs build OK with this change.
Acked-by: Stephen Warr
Hi Tom,
On 30 July 2015 at 15:09, Tom Warren wrote:
>
> Removed NS16550_COM1 #define, not used since there's no SPL for T210
> Also changed the number of USB controllers to 1 as only USBD is used.
>
> Signed-off-by: Tom Warren
> ---
> include/configs/p2571.h | 7 +--
> 1 file changed, 1 ins
On 30 July 2015 at 14:57, Tom Warren wrote:
> All T114+ Tegra boards should be using the Kconfig
> TEGRA114_SPI switch. Remove it from include/config
> and put it into defconfig. Also removed unused
> TEGRA114_SPI_CTRLS from T114+ configs.
>
> All Tegra SoCs build OK with this change.
>
> Signed-o
On 30 July 2015 at 14:34, Stephen Warren wrote:
> From: Stephen Warren
>
> Add a comment block to the top of each generated Tegra pinmux header file
> indicating that the file was auto-generated, should not be manually
> edited, and with a pointer to the tool and command used to generate it.
>
>
Simon,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Thursday, July 30, 2015 2:33 PM
> To: Tom Warren
> Cc: U-Boot Mailing List; Tom Warren; Stephen Warren
> Subject: Re: [PATCH] Tegra: P2571: Clean up config file
>
> Hi Tom,
>
> O
Hi Marek,
Le mercredi 29 juillet 2015 à 19:01 +0200, Marek Vasut a écrit :
> On Wednesday, July 29, 2015 at 04:41:53 PM, Hans de Goede wrote:
> > On 29-07-15 15:32, Paul Kocialkowski wrote:
> > > This series is based off the following patch:
> > > * drivers: hierarchize drivers Kconfig menu
> > >
Extend ehci-mx6 usb driver to support imx7d usb
Signed-off-by: Adrian Alonso
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-mx6.c | 125
2 files changed, 92 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/host/Makefile b/drive
* Add pmic pfuze3000 support, implement power_pfuze3000_init to be
used in power_init_board callback function.
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses
Pfuze 3000 as product name for the pm
* Add mxc_gpio support for imx7d SoC
* Use CONFIG_MX7 to extend mxc gpio driver support for imx7d
Signed-off-by: Peng Fan
Signed-off-by: Adrian Alonso
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
arch/arm/include/asm/arch-mx7/gpio.h | 12
drivers/gpio/m
* Ocotp of i.MX7D has different operation rule.
This patch is to add support for i.MX7D ocotp.
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
Signed-off-by: Ye.Li
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
drivers/misc/mxc_ocotp.c | 74 +++
* Add thermal driver support for imx7 SoC
read_cpu_temperature is SoC dependent
* Redefine config macro to support imx7 and imx6 SoC
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
---
Changes for V2:
- Rework patch so it can be applyed on top of patch
imx6: standardise OCOTP and fuse c
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slices.
Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot R
* Add timer support for imx7d SoC
Signed-off-by: Adrian Alonso
---
Changes for V2: Split from patch imx: imx7d: initial arch level support
Changes for V3: Resend
Changes for V4: Resend
arch/arm/imx-common/timer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/a
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