On Mon 2015-07-27 10:33:51, Masahiro Yamada wrote:
> Hi Pavel,
>
>
> 2015-07-27 3:38 GMT+09:00 Pavel Machek :
> > Hi!
> >
> >> We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
> >> devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
> >> away the ugly logic in incl
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.
Signed-off-by: Bin Meng
---
drivers/pci/pci-uclass.c | 4
1 file changed, 4 deletions(-)
diff --git
Currently Intel queensbay fsp initializes a CAR size with only 4KiB,
which is not enough when dm pci is enabled before relocation. Change
arch/x86/start.s to reserve a small size before fsp_init() is called
and some bigger size after fsp_init() which can be configured via
the exisiting CONFIG_MALLO
Increase CONFIG_MALLOC_F_LEN so that dm pci does not fail with -ENOMEM
before relocation. This makes pci uart work again on Intel Crown Bay.
Signed-off-by: Bin Meng
---
arch/x86/cpu/queensbay/Kconfig | 3 +++
arch/x86/cpu/queensbay/tnc.c | 13 +
arch/x86/dts/crownbay.dts |
With driver model, probing pci bus is all done on a lazy basis,
as needed. On x86, pci bus is the fundamental device that needs
to work before any other peripherals. In order to have a working
pci before any other pci devices can be initialized, we need
explicitly trigger the pci bus configuration.
Correct two typos and mention how pci bus will be probed.
Signed-off-by: Bin Meng
---
doc/driver-model/pci-info.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt
index 63efcb7..cf69167 100644
--- a/doc/dri
Hi Simon,
With driver model pci conversion on x86 boards, we now missed the call
to board_pci_pre_scan() and board_pci_post_scan() which are called in
the non-dm path. For example, board_pci_post_scan() in
arch/x86/lib/fsp/fsp_common.c is not called to do any work as
requested by FSP after pci enu
Dear Yegor,
In message <1437979451-14060-1-git-send-email-yegorsli...@googlemail.com> you
wrote:
>
> Enable DTS support (CONFIG_OF_LIBFDT), create ft_board_setup()
> stub and select CONFIG_FIT in defconfig.
...
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> + return 0;
> +}
What is the
From: Yegor Yefremov
Enable DTS support (CONFIG_OF_LIBFDT) and select
CONFIG_FIT in defconfig.
Signed-off-by: Yegor Yefremov
---
Changes:
v2: remove unused ft_board_setup() and CONFIG_OF_BOARD_SETUP
configs/am3517_evm_defconfig | 1 +
include/configs/am3517_evm.h | 2 ++
2 files chang
On Mon, Jul 27, 2015 at 10:44 AM, Wolfgang Denk wrote:
> Dear Yegor,
>
> In message <1437979451-14060-1-git-send-email-yegorsli...@googlemail.com> you
> wrote:
>>
>> Enable DTS support (CONFIG_OF_LIBFDT), create ft_board_setup()
>> stub and select CONFIG_FIT in defconfig.
> ...
>> +int ft_board_s
This switches the Integrator boards over to using the device model
for its serial ports.
Cc: Masahiro Yamada
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Moved CONFIG_DM and CONFIG_DM_SERIAL to Kconfig selects
- Moved CONFIG_SYS_MALLOC_F_LEN to Kconfig option
---
arch/arm/Kconfig
This switches the Integrator boards over to using the device model
for its serial ports.
Cc: Masahiro Yamada
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Moved CONFIG_DM and CONFIG_DM_SERIAL to Kconfig selects
- Moved CONFIG_SYS_MALLOC_F_LEN to Kconfig option
---
arch/arm/Kconfig
Hi Stefano, Marek,
On Sun, Jul 26, 2015 at 12:50:56PM +0200, Stefano Babic wrote:
> Hi Marek,
>
> On 26/07/2015 12:35, Marek Vasut wrote:
> > On Sunday, July 26, 2015 at 11:36:11 AM, Stefano Babic wrote:
> >> Hi Nikita, Marek,
> >>
> >> On 26/07/2015 10:17, Nikita Kiryanov wrote:
> >>> On Thu, Ju
Hi Lukasz,
On 04/24/2015 05:48 PM, Lukasz Majewski wrote:
> Hi Michal,
>
>> From: Siva Durga Prasad Paladugu
>>
>> Dont perform reset at the end of thor download
>> if configured to do reset off.
>> Reset may not be required in all cases and hence
>> provided an option to do so.
>>
>> The case w
From: Miao Yan
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.
This
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng
---
arch/x86/dts/qemu-x86_i440fx.dts | 7 +++
arch/x86/dts/qemu-x86_q35.dts| 7 +++
configs/qemu-x86_defconfig | 2 ++
doc/README.x86
On Monday, July 27, 2015 at 09:05:03 AM, Pavel Machek wrote:
> On Mon 2015-07-27 10:33:51, Masahiro Yamada wrote:
> > Hi Pavel,
> >
> > 2015-07-27 3:38 GMT+09:00 Pavel Machek :
> > > Hi!
> > >
> > >> We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
> > >> devices, $(SPL_) and CON
Hi,
Le mercredi 22 juillet 2015 à 11:31 +0200, Hans de Goede a écrit :
> Hi,
>
> On 22-07-15 10:45, Paul Kocialkowski wrote:
> > This makes sunxi boards use the USB_EHCI_HCD Kconfig option instead of
> > defining
> > USB_EHCI as a config define. This allows for more flexibility in enabling
> >
Hi,
Le dimanche 26 juillet 2015 à 02:46 +0900, Masahiro Yamada a écrit :
> The menuconfig for drivers are getting more and more cluttered
> and unreadable because too many entries are displayed in a single
> flat menu. Use hierarchic menu for each category.
That looks like a valuable addition to
Hi,
On 27-07-15 14:31, Paul Kocialkowski wrote:
Hi,
Le mercredi 22 juillet 2015 à 11:31 +0200, Hans de Goede a écrit :
Hi,
On 22-07-15 10:45, Paul Kocialkowski wrote:
This makes sunxi boards use the USB_EHCI_HCD Kconfig option instead of defining
USB_EHCI as a config define. This allows for
2015-07-27 19:52 GMT+09:00 Marek Vasut :
> On Monday, July 27, 2015 at 09:05:03 AM, Pavel Machek wrote:
>> On Mon 2015-07-27 10:33:51, Masahiro Yamada wrote:
>> > Hi Pavel,
>> >
>> > 2015-07-27 3:38 GMT+09:00 Pavel Machek :
>> > > Hi!
>> > >
>> > >> We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. W
On Sun, Jul 26, 2015 at 03:18:13PM +0200, Stefano Babic wrote:
> mcx was not updated according to changes in
> NAND driver.
>
> Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini
--
Tom
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On Thu, Jul 23, 2015 at 08:31:56PM +0900, Masahiro Yamada wrote:
> The previous commit introduced a useful macro used in makefiles,
> which references to different variables (CONFIG_ or CONFIG_SPL_
> prefixed), in order to enable/disable features independently
> for each of images.
>
> Per-image
On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
> Commit e02ee2548afe ("kconfig: switch to single .config
> configuration") made the configuration itself pretty simple,
> instead, we lost the way to systematically enable/disable config
> options for each image independently.
>
>
On Sat, Jul 25, 2015 at 08:59:35PM +0800, Peng Fan wrote:
> Discard the empty video_set_lut function from platform video
> drivers.
>
> This commit "69d275458893eaec35229b589092c2a6bde5440f" introduces
> a weak function video_set_lut, so we do not need an strong function
> in platform drivers, wh
On Sun, Jul 26, 2015 at 03:18:15PM +0200, Stefano Babic wrote:
> Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini
--
Tom
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On Mon, Jul 27, 2015 at 11:10:58AM +0200, yegorsli...@googlemail.com wrote:
> From: Yegor Yefremov
>
> Enable DTS support (CONFIG_OF_LIBFDT) and select
> CONFIG_FIT in defconfig.
>
> Signed-off-by: Yegor Yefremov
Reviewed-by: Tom Rini
--
Tom
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On Sun, Jul 26, 2015 at 03:18:14PM +0200, Stefano Babic wrote:
> Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini
--
Tom
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Tom,
2015-07-28 0:08 GMT+09:00 Tom Rini :
> On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
>
>> Commit e02ee2548afe ("kconfig: switch to single .config
>> configuration") made the configuration itself pretty simple,
>> instead, we lost the way to systematically enable/disable co
On Tue, Jul 28, 2015 at 12:19:07AM +0900, Masahiro Yamada wrote:
> Tom,
>
>
> 2015-07-28 0:08 GMT+09:00 Tom Rini :
> > On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
> >
> >> Commit e02ee2548afe ("kconfig: switch to single .config
> >> configuration") made the configuration itse
Hi Marek, other USB guys,
I noticed commit dc9cdf859e11de (usb: dwc3: Add DWC3 controller driver
support) was pulled into the mainline a few days ago.
Now we have two drivers with similar names.
- drivers/usb/dwc3/
- drivers/usb/host/xhci-dwc3.c
Are they the same hardware, or completely dif
2015-07-26 17:49 GMT+09:00 Marek Vasut :
> On Sunday, July 26, 2015 at 10:26:45 AM, Masahiro Yamada wrote:
>> The board-specific linker script board/vpac270/u-boot-spl.lds
>> obstructs further cleanup. This board has not been converted to
>> Generic Board yet in spite of the long-term warning. Re
On 24 July 2015 at 10:33, Michal Suchanek wrote:
> Hello,
>
> it seems extlinux.conf is pushed as *the* u-boot configuration.
>
> As in it is promoted by many people and its flexibility is praised.
>
> It overrides boot script when both are present.
>
> However,
>
> 1) it is not documented. There
Hello Scott,
On 18.07.2015 03:07, Vladimir Zapolskiy wrote:
> The change adds support of LPC32xx SLC NAND controller.
>
> LPC32xx SoC has two different mutually exclusive NAND controllers to
> communicate with single and multiple layer chips.
>
> This simple driver allows to specify NAND chip ti
Hi,
Le 24/07/2015 17:22, Ash Charles a écrit :
On Fri, Jul 24, 2015 at 7:04 AM, Tom Rini wrote:
Can you give us more details on the exact nature of the failure? Thanks!
Oh sorry--that wasn't clear! The boards appear to get stuck in SPL
before anything can be printed to the console. Basicall
Hi Andre,
On 27 July 2015 at 11:08, Andre Przywara wrote:
>
> Hi Simon,
>
> On 24/06/15 00:29, Simon Glass wrote:
> > diff --git a/doc/README.rockchip b/doc/README.rockchip
> > new file mode 100644
> > index 000..a34e198
> > --- /dev/null
> > +++ b/doc/README.rockchip
>
>
>
> > +
> > +Fu
Hi,
On 23 July 2015 at 10:51, Stephen Warren wrote:
> From: Thierry Reding
>
> Signed-off-by: Thierry Reding
> Signed-off-by: Tom Warren
> Signed-off-by: Stephen Warren
> ---
> Simon,
>
> When Thierry first posted this patch, you responded:
>
>> > + parent = fdt_parent_offset(blob, node
Hi Simon,
On 24/06/15 00:29, Simon Glass wrote:
> diff --git a/doc/README.rockchip b/doc/README.rockchip
> new file mode 100644
> index 000..a34e198
> --- /dev/null
> +++ b/doc/README.rockchip
> +
> +Future work
> +===
> +
> +Immediate priorities are:
> +
> +- MMC support (in U-
Le lundi 20 juillet 2015 à 17:13 +0200, Heiko Schocher a écrit :
> Hello Paul,
>
> Am 20.07.2015 um 15:30 schrieb Paul Kocialkowski:
> >> I am just on the jump into my holidays, so I have not yet the time
> >> to test it ... I want to try it for all builds with the scripts
> >> I posted with my v2
On Monday, July 27, 2015 at 05:37:52 PM, Masahiro Yamada wrote:
> Hi Marek, other USB guys,
Hi!
> I noticed commit dc9cdf859e11de (usb: dwc3: Add DWC3 controller driver
> support) was pulled into the mainline a few days ago.
>
>
> Now we have two drivers with similar names.
>
>
> - drivers/us
From: Thierry Reding
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Signed-off-by: Thierry Reding
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
---
arch/arm/mach-tegra/board.c | 2 +-
1 file changed, 1 inser
From: Thierry Reding
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restr
From: Thierry Reding
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Signed-off-by: Thierry Reding
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
---
include/
From: Sylvain Lemieux
This series of patches bring miscellaneous enhancement
and update to the existing lpc32xx support in u-boot.
Refer to each individual patches for details on the specific change.
The patch adding the LPC32xx MAC and SMSC RMII phy support
should be applied first (for patch
From: Sylvain Lemieux
Add LPC32xx GPIO interface macro for pin mapping.
Signed-off-by: Sylvain Lemieux
---
arch/arm/include/asm/arch-lpc32xx/gpio_grp.h | 40
1 file changed, 40 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
diff --g
From: Sylvain Lemieux
The HCLK is not constant and can take different value; use the api function to
get the value of the HCLK for the I2C clock high and low computation.
Signed-off-by: Sylvain Lemieux
---
drivers/i2c/lpc32xx_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
From: Sylvain Lemieux
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).
To be compatible with the original U-Boot code, when the "addr" parameter is 0,
a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain Lemieux
---
arch/arm/
From: Sylvain Lemieux
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User
manual" Rev. 3 - 22 July 2011).
Signed-off-by: Sylvain Lemieux
---
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +-
arch/arm/include/asm/arch-lpc32xx/mux.
From: Sylvain Lemieux
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when
parameters alen = 0 and len = 0.
Signed-off-by: Sylvain Lemieux
---
drivers/i2c/lpc32xx_i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc3
From: Sylvain Lemieux
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when
parameters alen != 0 and len = 0.
Signed-off-by: Sylvain Lemieux
---
drivers/i2c/lpc32xx_i2c.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/lpc32xx
On 07/24/2015 04:00 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegr
From: Sylvain Lemieux
Add support to specify the Ethernet buffer base address;
if none are supply by the board, the default value is use (from existing code).
Signed-off-by: Sylvain Lemieux
---
drivers/net/lpc32xx_eth.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
On 07/24/2015 04:00 PM, Tom Warren wrote:
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
diff --git a/arch/arm/dts/tegra210.dtsi b/arch/a
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Monday, July 27, 2015 10:53 AM
> To: Tom Warren
> Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
> tomcwarren3...@gmail.com
> Subject: Re: [U-Boot] [PATCH V3 3/6] ARM: Tegra210: Add SoC c
On 07/24/2015 04:01 PM, Tom Warren wrote:
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
diff --git a/include/configs/venice2.h b/incl
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Monday, July 27, 2015 10:55 AM
> To: Tom Warren
> Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
> tomcwarren3...@gmail.com
> Subject: Re: [U-Boot] [PATCH V3 4/6] ARM: Tegra210: Add suppo
On 07/24/2015 04:00 PM, Tom Warren wrote:
This patch series adds support for the Tegra210
SoC and the P2571 board. Most of the T210 info
is identical to T124 at this point, so I just
cloned Venice2/Jetson-TK1 board files and T124
header/SoC code. Pinmux is the major area of
difference at this tim
Thanks, Stephen!
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Monday, July 27, 2015 11:01 AM
> To: Tom Warren
> Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
> tomcwarren3...@gmail.com
> Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 i
On 07/27/2015 09:36 AM, York Sun wrote:
>
>
> On 07/26/2015 03:20 AM, Stefano Babic wrote:
>> I apply it to u-boot-imx - merging into mainline, we will have more
>> chances to get it tested on PowerPc.
>>
>> Applied to u-boot-imx, thanks !
>>
>
> Sorry I didn't see this thread until Stefano CC
On 27/07/2015 20:15, York Sun wrote:
>
>
> On 07/27/2015 09:36 AM, York Sun wrote:
>>
>>
>> On 07/26/2015 03:20 AM, Stefano Babic wrote:
>>> I apply it to u-boot-imx - merging into mainline, we will have more
>>> chances to get it tested on PowerPc.
>>>
>>> Applied to u-boot-imx, thanks !
>>>
>>
On 05/17/2015 11:31 PM, Priyanka Jain wrote:
> sw variable in checkboard function is storing vbank value
> which can only take 4-bit value.
> So check of sw value for if greater than 7 is redundant.
>
> Signed-off-by: Priyanka Jain
> ---
> board/freescale/t104xrdb/t104xrdb.c |5 +
> 1
On 07/15/2015 12:34 AM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> T4160 and T4080 support same serdes options, which serdes 2 & 3 support 8
> Lanes, same as T4240, but serdes 1 & 4 support only 4 Lanes, Lanes A, B,
> C, D are not available, updated the serdes table accordingly with
> som
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Enable optional raw initrd support to allow boot using an initrd.
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
Doesn't arch/arm/include/asm/config.h set
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Max Krummenacher
Enable CONFIG_IP_DEFRAG and set CONFIG_TFTP_BLOCKSIZE to 16384.
This increases the tftp download speed considerably.
While at it enable CONFIG_TFTP_TSIZE which limits the progress bar to
fifty '#' independent of the download
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Unfortunately currently both Apalis T30 as well as Colibri T30 crash
upon starting USB host support. This is due to the following patch not
having taken into account that our T30 device trees were defaulting to
peripheral only
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
This patch set is an assortment of tegra fixes/enhancements distilled
straight from our downstream integration work.
Other than the comments I already made and other than the NAND read_byte
change (which I don't know enough
On Tue, 2015-07-21 at 00:35 +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> Integrate cache alignment bounce buffer to workaround issues as follows:
>
> Loading file '/boot/zImage' to addr 0x0100 with size 4499152
> (0x0044a6d0)...
> ERROR: v7_dcache_inval_range - start address is
On Tue, 2015-07-21 at 00:35 +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> Fix PIO read_byte() implementation not only used for the legacy READ ID
> but also the PARAM command now required for proper ONFI detection.
>
> This fix is inspired by Lucas Stach's Linux Tegra NAND driver of
There's no reason why simple-bus driver can not be used in SPL,
in fact it is necessary to get SoCFPGA SPL probe the cadence
SPI driver. So drop the restriction.
Signed-off-by: Marek Vasut
Cc: Simon Glass
---
drivers/core/Makefile | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/cor
The driver variable name is eth_sandbox, which is probably a copy-paste
mistake. Fix it.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Joe Hershberger
---
drivers/net/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/design
Add the OF compatible property to match the SoCFPGA GMAC.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Joe Hershberger
---
drivers/net/designware.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bcae842..cadf3c8 100644
--- a/driv
Add code to aid tracking down cache alignment issues.
In case DEBUG is defined in the cache.c, this code will
check alignment of each attempt to flush/invalidate data
cache and print a warning if the alignment is incorrect.
If DEBUG is not defined, this code is optimized out.
Signed-off-by: Marek
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
---
drivers/fpga/socfpga.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/
The driver didn't stop the bounce buffer in case a data transfer
failed. This would lead to memory leakage if the communication
between the CPU and the card is unreliable. Add the missing call
to stop the bounce buffer.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Tom Ri
In case the data transfer failure happens, instead of returning
immediatelly, make sure the DMA is disabled, status register is
cleared and the bounce buffer is stopped.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Tom Rini
---
drivers/mmc/dw_mmc.c | 16 +--
Endless timeouts are bad, since if we get stuck in one, we have no
way out. Zap this one by implementing proper timeout.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Tom Rini
---
drivers/mmc/dw_mmc.c | 19 +--
1 file changed, 17 insertions(+), 2 deletio
Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Tom Rini
---
arch/arm/mach-socfpga/include/mach/dwmmc.
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.
So fix it such that we move these into socfpga.dtsi and
Add alias for the SD/MMC controller, so it can be located by U-Boot OF support.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
---
arch/arm/dts/socfpga.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 3a3fb4a..e17e9f4 100644
--- a/
Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.
Signed-off-by: Marek Vasut
Cc: Simon Glass
---
drivers/gpio/Makefile | 1 +
drivers/gpio/dwapb_gpio.c | 167 ++
2 files changed, 168 insertions(+)
cr
Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Dinh Nguyen
---
include/configs/socfpga_arria5.h | 2 +-
include/configs/socfpga_common.h | 6 ++
include/configs/socfpga_cyclone5.h | 2 +-
3 files changed, 8 insertions(+),
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
---
board/altera/socfpga/Makefile | 2 +-
board/altera/socfpga/qts/Makefile
Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b/arch/arm/mach-socfpga/i
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
Makefile
This file is absolutelly positively board specific, so move it
into the correct place.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/sdram_config.h | 100 --
board/altera/socfpga/qts/sdram_config.h | 100 ++
drivers/ddr/altera
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 ---
arch/arm/
This series fixes the SPL support on SoCFPGA and cleans up the DDR
init code such that it is becoming remotely mainlinable. After this
series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
There is still work to be done, but I'd like to start picking it up
so it can land in 2015.10
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 +
arch/arm/mach-socfpga/reset_manager.c | 13 +
2 files changed, 14 inser
From: Dinh Nguyen
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen
Acked-by: Marek Vasut
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0
Get rid of this cryptic typedef and replace it with explicit struct cm_config.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/clock_manager.c | 2 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 +++---
arch/arm/mach-socfpga/spl.c| 2 +-
3 fil
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any p
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_conf
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Tom Rini
---
drivers/ddr/altera/sdram.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
It is sufficient to pass in the scan chain ID into the function to determine
the remaining two parameters, so drop those params and determine them locally
in the function. The big-ish switch in the function is temporary and will be
replaced by a proper function call in subsequent patch.
Signed-off
Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b
This function is never used outside of scan_manager.c , so make it static.
Zap the prototype in scan_manager.h and move the documentation above the
function. Make the documentation kerneldoc compliant.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/scan_manager.h | 11
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 2 +-
arch/arm/mach-socfpga/spl.c
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
arch/arm/mach-socfpga/r
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: Marek Vasut
---
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