From: Thierry Reding
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch def
From: Thierry Reding
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra124.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
From: Thierry Reding
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3:
- Use driver model for the PMIC
drivers/power/Makefile | 1 +
drivers/power/as3722.c | 264 +++
From: Thierry Reding
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes
From: Thierry Reding
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/cpu/tegra-common/Makefile | 1 +
arch/arm/cpu/tegra-common/powergate.c
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra124.dtsi | 66 ++
1 file cha
From: Thierry Reding
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.
Tegra20 and Tegra30 also provide w
From: Thierry Reding
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.
This is based on the Linux kernel driver, origina
From: Thierry Reding
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
From: Thierry Reding
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra30.dtsi | 74 +
include/dt-bindings/clock/tegra30-car
From: Thierry Reding
When DEBUG is set, output memory region used for malloc().
Signed-off-by: Thierry Reding
Acked-by: Simon Glass
Signed-off-by: Simon Glass
---
Changes in v3: None
common/dlmalloc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/dlmalloc.c b/common/dlmallo
From: Thierry Reding
According to the top-level README file, this configuration setting can
be used to override the number of receive buffers that an ethernet NIC
uses.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
drivers/net/rtl8169.c | 6 +-
1 file
From: Thierry Reding
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
From: Thierry Reding
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Ch
From: Thierry Reding
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_S
From: Thierry Reding
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glas
From: Thierry Reding
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3:
- Remove cache-line
From: Thierry Reding
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so e
From: Thierry Reding
This network interface card in found on the NVIDIA Jetson TK1.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
drivers/net/rtl8169.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index
From: Thierry Reding
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is
This is v7 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html
v4: https://patchwork.ozlabs.org/patch/407411/
v5: https://patchwork
This patch adds documentation for Odroid-XU3. This documentation is
based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak.
The documentation includes basic information about boot media layout,
environment, partition layout, and the instruction to burn the u-boot
image to boot media
This patch fixes wrong GPIO information such as GPIO bank, table which
is used to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
Cc: Minkyu Kang
Cc: Lukasz Majewski
---
Changes for v4:
- None
Changes
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
Cc: Minkyu Kang
Cc: Lukasz Majewski
---
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros
From: Thierry Reding
Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable declaration section to a separate line (rather than the
one with the opening brace) and keeps the function signature on
From: Thierry Reding
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra124-jets
From: Thierry Reding
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra20-trimslice.d
From: Thierry Reding
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra30.dtsi
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
---
Changes in v3: None
arch/arm/dts/tegra20.dtsi | 59 +
include/dt-
On 31 October 2014 02:55, Akshay Saraswat wrote:
> This patch intends to add a new proid for Exynos5800 which is a
> variant of Exynos5420. Product id for Exynos5800 is 0x5422.
> Both Exynos5420 and Exynos5800 are pin to pin compitable. This
> gives us an advantage of reusing Exynos5420 clock, pin
On 31 October 2014 02:55, Akshay Saraswat wrote:
> We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi
> differs from Peach-Pit in configuration factors like display
> resolution, memory size, SoC version etc.
>
> Signed-off-by: Alim Akhtar
> Signed-off-by: Akshay Saraswat
> ---
> Change
On 31 October 2014 02:55, Akshay Saraswat wrote:
> This adds following things :
> - New config and defconfig for Peach-Pi board.
> - Alterations in Kconfig and MAINTAINERS.
> - Addition of CONFIG_EXYNOS5800.
> - ADdition of exynos5800-peach-pi in dts list.
>
> Signed-off-by: Akshay Saraswat
> ---
On 31 October 2014 02:55, Akshay Saraswat wrote:
> From: Alim Akhtar
>
> As per Exynos5800 UM ver 0.00 section 17.13.2.1
> CONCONTROL register bit 3 [update_mode], Exynos5800 does not
> support the PHY initiated update. And it is recommanded to
> set this field to 1'b1 during initialization. This
On 31 October 2014 02:55, Akshay Saraswat wrote:
> Since, not every board may have all memory channels configured
> and all available banks of DMC used, we wish to refactor configs
> for Memory Bank size and numbers as per board memory config.
> For Example, Peach-Pit has 2GB memory and will be us
On 31 October 2014 02:55, Akshay Saraswat wrote:
> Add a 4G configuration and choose it based on the number of banks
> declared in config file. A board with 4 SDRAM banks declared (as
> per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.
>
> Signed-off-by: Doug Anderson
> Signed-off-b
On 31 October 2014 02:55, Akshay Saraswat wrote:
> From: Vadim Bendebury
>
> Exynos5800 IROM has a different, from 5250 and 5420, prototype of the
> usb_copy() function. Luckily the earlier version did not expect any
> arguments, which means the same code could be used with old and new
> SoCs, th
Hi Akshay,
On 31 October 2014 02:55, Akshay Saraswat wrote:
> Now we are adding a new Peach-Pi board which is a variant of Peach-Pit
> and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420,
> hence, most of the hardware config and settings are reused for this board.
>
> Changes
Hi Martin,
On 30 October 2014 00:45, Martin Dorwig wrote:
> Am Mittwoch, 29. Oktober 2014, 13:03:41 schrieben Sie:
>> Hi Martin,
>>
>> On 28 October 2014 07:23, Martin Dorwig wrote:
>> > Hello,
>> > after updating u-boot from git v2014.10
>> > i just noticed that my standalone application outpu
On 12 November 2014 06:35, Christian Gmeiner
wrote:
> Some filesystems have a UUID stored in its superblock. To
> allow using root=UUID=... for the kernel command line we
> need a way to read-out the filesystem UUID.
>
> changes rfc -> v1:
> - make the environment variable an option parameter. If
Hi Tom,
On 24 October 2014 12:50, Tom Rini wrote:
> On Thu, Oct 23, 2014 at 06:58:54PM -0600, Simon Glass wrote:
>
>> Add an additional function for adding information to the device tree before
>> booting. This permits additions which are not board-specific.
>>
>> Signed-off-by: Simon Glass
>> A
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.
Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to d
Hi,
On 29 October 2014 13:08, Simon Glass wrote:
> This series adds driver model support for serial and GPIO for the Atmel AT91
> series. The at91sam9260-based Snapper 9260 is converted over as an example.
>
> For both drivers the old behaviour is retained, so driver model becomes
> optional, not
On 11 November 2014 14:58, Tom Rini wrote:
> When saving binary files we likely want to keep any .img files that have
> been generated as well.
>
> Signed-off-by: Tom Rini
Acked-by: Simon Glass
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Hi,
On 4 November 2014 08:21, Weiß Christoph wrote:
> Well, for me it works with type kernel and loading it to a higher RAM address
> than the load address and entry point. I'm not exactly sure if kernel_noload
> is supported with Tegra. Is type kernel completely wrong?
I'm just not sure why y
From: Shaohui Xie
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;
Signed-off-by: Shaohui Xie
---
board/freescale/b4
This warning appears even though it seems that the compiler could work it
out. Fix it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a4e639d..3583619 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.
Signed-off-by: Masahiro Yamada
---
Makefile
In Kbuild, the build system generally descends into each directory
from its parent directory, but SOC directory is one of the rule
violations.
My motivation of this series is to make further refactoring possible.
You might perhaps wonder if the build system works equivalently
especially with 3/4
From: Shaohui Xie
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
From: Suresh Gupta
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_am
Some tegra makefiles only contain a dummy line to generate
a built-in.o. Let's do not descend into such directories.
Signed-off-by: Masahiro Yamada
Cc: Tom Warren
Cc: Stephen Warren
---
arch/arm/cpu/armv7/Makefile | 3 ---
arch/arm/cpu/armv7/tegra114/Makefile | 21 -
Use "obj-$(CONFIG_FOO) += foo/" where it is possible.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/arm1136/Makefile | 3 ++-
arch/arm/cpu/arm1176/Makefile | 3 ++-
arch/arm/cpu/arm720t/Makefile | 6 --
arch/arm/cpu/arm920t/Makefile | 7 ++-
arch/arm/cpu/arm926ejs/Makefile
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada
Cc: Simon Glass
---
arch/x86/cpu/Makefile | 2 +-
arch/x86/cpu/coreboot/
On 12 November 2014 20:28, Masahiro Yamada wrote:
> Some tegra makefiles only contain a dummy line to generate
> a built-in.o. Let's do not descend into such directories.
>
> Signed-off-by: Masahiro Yamada
> Cc: Tom Warren
> Cc: Stephen Warren
Acked-by: Simon Glass
__
On 12 November 2014 20:28, Masahiro Yamada wrote:
> The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
> are redundant because the build system descends into the directory
> only when CONFIG_SYS_COREBOOT is defined.
>
> Signed-off-by: Masahiro Yamada
> Cc: Simon Glass
> ---
From: Suresh Gupta
SerDes2 lanes EFGH either go to SFP or AMC riser card slot2.
By default AMC will be configured even if no hwconfig is specified.
To enable XFI via SFP use the below hwconfig:
fsl_b4860_serdes2:sfp_amc=sfp
Signed-off-by: Suresh Gupta
Signed-off-by: Poonam Aggrwal
Sig
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Added missing print_cpuinfo() call in coreboot.c
arch/x86/cpu/coreboot/coreboot.c | 5 +
arch/x86/cpu/cpu.c
Hi,
On 12 November 2014 20:46, Simon Glass wrote:
> This implementation has a 'cpu' prefix and returns a pointer to the string,
> avoiding the need for copying.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v3:
> - Added missing print_cpuinfo() call in coreboot.c
From: Shaohui Xie
Since xfi has no phy, we delete the property "phy-handle" and use
a "fixed-link" property for a xfi port.
Signed-off-by: Shaohui Xie
---
board/freescale/b4860qds/eth_b4860qds.c | 38 +
1 file changed, 38 insertions(+)
diff --git a/board/freesc
On 10 November 2014 18:00, Simon Glass wrote:
> For some CPUs, having malloc() available very early is useful. There is no
> reason to delay this since early malloc is allocated before board_init_f()
> is called.
>
> Move early malloc() init nearer to the start of the init sequence.
>
> Signed-off
On 10 November 2014 18:00, Simon Glass wrote:
> Sometimes an array can be of variable size up to a maximum. Add a helper
> function to decode this.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> include/fdtdec.h | 16
> lib/fdtdec.c | 20 +++
On 10 November 2014 18:00, Simon Glass wrote:
> For board IDs a common approach is to set aside several GPIOs for use in
> determining the board ID. This can provide information about board features
> and the revision.
>
> Add a function that turns a list of GPIOs into an integer by assigning
> ea
On 10 November 2014 18:00, Simon Glass wrote:
> In general we can't store things in the data section until we have inited
> SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move
> the pointer to global_data so that it will work on all platforms.
>
> Without this fix the seria
On 11 November 2014 01:47, Bin Meng wrote:
> On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass wrote:
>> Many of the x86 CONFIG options will be common across different boards. Move
>> them to a common file.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Move some features out of th
On 12 November 2014 20:27, Simon Glass wrote:
> This warning appears even though it seems that the compiler could work it
> out. Fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
Applied to u-boot-x86.
___
On 10 November 2014 18:00, Simon Glass wrote:
> Newer Intel chips require a Management Engine which requires a particular
> format for the SPI flash that contains the boot loader. Add a tool that
> supports creating and modifying these ROM images.
>
> This tool is from Chrome OS but has been clean
On 11 November 2014 02:34, Bin Meng wrote:
> On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass wrote:
>> These are no-longer needed so drop them.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Remove definition of find_fdt() also
>> - Remove prepare_fdt() also
>>
>> arch/x86/inclu
On 12 November 2014 20:47, Simon Glass wrote:
> Hi,
>
> On 12 November 2014 20:46, Simon Glass wrote:
>> This implementation has a 'cpu' prefix and returns a pointer to the string,
>> avoiding the need for copying.
>>
>> Signed-off-by: Simon Glass
>> Reviewed-by: Bin Meng
>> ---
>>
>> Changes i
On 11 November 2014 02:32, Bin Meng wrote:
> Reviewed-by: Bin Meng
>
Applied to u-boot-x86.
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At present U-Boot's x86 support requires Coreboot to run first, starting
up the CPU and then setting up SDRAM and video among other tasks. U-Boot
then runs as a payload. Notably U-Boot does not handle the ACPI fun on
x86 where the kernel can call back into the 'BIOS' to perform certain tasks.
This
Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass
---
Changes in v3:
- Adjust PCI setup code to fit with new generic cpu PCI code
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 6
a
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Change comm
This is no-longer used, so drop it.
Signed-off-by: Simon Glass
---
Changes in v3:
- Split out CONFIG_INTEL_CORE_ARCH removal patch
Changes in v2: None
arch/x86/cpu/interrupts.c | 28
1 file changed, 28 deletions(-)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x8
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c| 5 +
arch/x86/c
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 16
1 file changed, 16 insertions(+)
diff --git a/a
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Expand the comment about preserving ebp
- Move SIPI c
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be bo
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.
Signed-off-by: Simon Glass
---
Changes in v3:
- Callpci_setup_type1() in early PCI setup
Changes in v2:
- Split out new patch to support use fo PCI before relocation
arch/x86/cpu/pci.c |
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.
So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it woul
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Fix mangled cros_ec reg property
arch/x86/cpu/iv
This function can probably be used on all x86 boards, so move it into the
common file.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 24
arch/x86/cpu/cpu.c | 24
2 files
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.
In this implementation, board files sh
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 141 +++
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 3 ++
arch/x86/
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 130 ++
arch/x86/include/asm/arch-ivybridge/model_206ax.h
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.
For this CPU we know the frequency, so add another special case for now.
Signed-off-by: Simon Glass
---
Changes in v3:
- Try another approach for fixing the timer
Change
Allow an empty ROM to be created, without needing to provide a descriptor.
The descriptor is not needed on some x86 boards.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to allow ifdtool to create an empty ROM
Changes in v2: None
tools/ifdtool.c | 2 +-
1 file changed, 1 inser
Enable GPIO support and provide the required GPIO setup information to
the driver.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/link.dts | 3 +
board/google/chromebook_link/link.c | 107
include/configs
These are available on other architectures. Make them available on x86 also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/io.h | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/x86/include/as
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/msr.h |
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bu
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 4 ++--
arch/x86/cpu/coreboot/i
On 11/13/2014 10:32 AM, Hyungwon Hwang wrote:
> This is v7 of the patchset adding support Odroud XU3 board.
>
> link to the previous version:
> v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
> v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html
> v4: https:
On Thu, Nov 13, 2014 at 1:42 PM, Simon Glass wrote:
> Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
> seems to take up to 50ms which is much too long.
>
> For this CPU we know the frequency, so add another special case for now.
>
> Signed-off-by: Simon Glass
> ---
>
On Thu, Nov 13, 2014 at 1:42 PM, Simon Glass wrote:
> This is no-longer used, so drop it.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3:
> - Split out CONFIG_INTEL_CORE_ARCH removal patch
>
> Changes in v2: None
>
> arch/x86/cpu/interrupts.c | 28
> 1 file c
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