At present U-Boot's x86 support requires Coreboot to run first, starting
up the CPU and then setting up SDRAM and video among other tasks. U-Boot
then runs as a payload. Notably U-Boot does not handle the ACPI fun on
x86 where the kernel can call back into the 'BIOS' to perform certain tasks.
This Coreboot + U-Boot method is used for link (Chromebook Pixel) and it
works fairly well.
However this does not remove the need for all x86-specific init in U-Boot.
For each generation of chipset we need to adjust U-Boot to make it work,
albeit sometimes not a lot. In any case this work has not been done so the
x86 port risks being stranded.
There are also a few disadvantages to using two separate boot loaders. When
Coreboot decides not set to up the video card, it is not possible for U-Boot
to go back and do this.
Building an image which has both boot loaders in itis a little tricky,
particularly with the binary blobs that are required.
After some experimentation prompted by a discussion at ELCE, it was found
that while x86 is somewhat different to most of the other architectures that
U-Boot supports, it actually fits the model fairly well. There is nothing
magic about getting the platform running. Also it turns out that x86 likes
running before relocation with no DRAM, using global_data, relocating and
then starting up the full U-Boot, all within the same image (Coreboot
splits this into three programs which run one after the other). Perhaps
this is because U-Boot was conceived before the more modern SoCs with SRAM,
FAT file system code in the ROM, etc.
This series contains a basic port of U-Boot to a bare x86 environment. It
would be targeted at some generally available board, such as the Minnowmax,
except that it doesn't seem to be generally available, at least for me. So
while that remains a goal, for now the port targets link. It is already
supported in U-Boot and the platform is well understood.
The following are implemented in this series:
- ivybridge support with some peripherals enabled
- SDRAM init using a binary blob (Memory Reference Code)
- Use of Intel Management Engine via another binary blob
- microcode update from device tree
- ifttool for creating ROMs of the required format (u-boot.rom)
- GPIO
Notably missing are:
- PCI device support (USB, SATA)
- Video support
- MTRR setup (for performance)
- Real time clock
- Chrome OS EC
- Documentation
- Links to binary blobs
These will be addressed in a follow-up series. Things like ACPI and SMI will
come later.
Unfortunately this series is quite long as it includes basic infrastructure
needed on x86. But it is a solid step forward: with this series, link boots
to a prompt.
This series is available at u-boot-x86/working
Changes in v3:
- Add a CONFIG_X86_RAMTEST option to enable the SDRAM test
- Add an option to control the inclusion of the Intel ME
- Add help for CONFIG_ENABLE_VMX
- Add new patch to allow ifdtool to create an empty ROM
- Adjust PCI setup code to fit with new generic cpu PCI code
- Assign hose->last_busno when calling pci_hose_scan()
- Callpci_setup_type1() in early PCI setup
- Change asm label to 1 (from 2)
- Enable Intel ME for chromebook_link
- Move pci_setup_type1() call to common pci file
- Rebase against x86/master
- Remove extra coreboot print_cpuinfo() implementation
- Split out CONFIG_INTEL_CORE_ARCH removal patch
- Try another approach for fixing the timer
- Use cpu_get_name() in report_paltform.c
- Use the CONFIG_HAVE_INTEL_ME option in the Makefile
Changes in v2:
- Add a common early_init file
- Add mrc.bin dependency for u-boot.rom build rule
- Add new patch to rename chromebook-x86 to coreboot
- Add new patch to tidy up timer code for Intel core architecture
- Adjust config to deal with changed x86-common.h
- Adjust to use asm/cpu.h header for cpuid
- Change commit message to indicate that SPDX license request is submitted
- Correct 'peripheral controller hub' to 'platform controller hub'
- Drop patch to move coreboot PCI into common cpu area
- Drop patch which removes the early_board_init() feature
- Expand the comment about preserving ebp
- Fix incorrect subl mnemonic in start.S
- Fix mangled cros_ec reg property
- Move SIPI code to after CAR init
- Move early init code into early_board_init
- Remove use of PCI_CPU_DEVICE and use PCH_DEV instead
- Split out new patch to support use fo PCI before relocation
- Use capitals for all #define declarations
Simon Glass (26):
x86: Allow timer calibration to work on ivybridge
x86: Drop old CONFIG_INTEL_CORE_ARCH code
x96: ifdtool: Allow creation of an empty ROM
x86: Add chromebook_link board
x86: Build a .rom file which can be flashed to an x86 machine
x86: Emit post codes in startup code for Chromebooks
x86: chromebook_link: Implement CAR support (cache as RAM)
x86: Refactor PCI to permit alternate init
x86: Support use of PCI before relocation
x86: ivybridge: Enable PCI in early init
x86: pci: Allow configuration before relocation
x86: ivybridge: Add early LPC init so that serial works
x86: Tidy up coreboot header usage
x86: Add clr/setbits functions
x86: Add msr read/write functions that use a structure
x86: ivybridge: Perform initial CPU setup
x86: ivybridge: Check BIST value on boot
x86: ivybridge: Perform Intel microcode update on boot
x86: dts: Add microcode updates for ivybridge CPU
x86: ivybridge: Add early init for PCH devices
x86: ivybridge: Add support for early GPIO init
x86: chromebook_link: Enable GPIO support
x86: Make show_boot_progress() common
x86: ivybridge: Add LAPIC support
x86: ivybridge: Implement SDRAM init
x86: Rename chromebook-x86 to coreboot
Makefile | 36 +-
arch/x86/Kconfig | 74 +-
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/coreboot/coreboot.c | 28 +-
arch/x86/cpu/coreboot/ipchecksum.c | 2 +-
arch/x86/cpu/coreboot/pci.c | 22 +-
arch/x86/cpu/coreboot/tables.c | 6 +-
arch/x86/cpu/cpu.c | 24 +
arch/x86/cpu/interrupts.c | 28 -
arch/x86/cpu/ivybridge/Kconfig | 172 +++++
arch/x86/cpu/ivybridge/Makefile | 16 +
arch/x86/cpu/ivybridge/car.S | 178 +++++
arch/x86/cpu/ivybridge/cpu.c | 357 ++++++++++
arch/x86/cpu/ivybridge/early_init.c | 145 ++++
arch/x86/cpu/ivybridge/early_me.c | 191 ++++++
arch/x86/cpu/ivybridge/lpc.c | 48 ++
arch/x86/cpu/ivybridge/me_status.c | 195 ++++++
arch/x86/cpu/ivybridge/microcode_intel.c | 151 +++++
arch/x86/cpu/ivybridge/pci.c | 60 ++
arch/x86/cpu/ivybridge/report_platform.c | 89 +++
arch/x86/cpu/ivybridge/sdram.c | 571 ++++++++++++++++
arch/x86/cpu/pci.c | 98 +++
arch/x86/cpu/start.S | 14 +-
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/link.dts | 125 ++++
arch/x86/dts/m12206a7_00000028.dtsi | 622 +++++++++++++++++
arch/x86/dts/m12306a9_00000017.dtsi | 750 +++++++++++++++++++++
arch/x86/include/asm/arch-coreboot/gpio.h | 5 -
arch/x86/include/asm/arch-ivybridge/gpio.h | 10 +
arch/x86/include/asm/arch-ivybridge/me.h | 356 ++++++++++
arch/x86/include/asm/arch-ivybridge/microcode.h | 20 +
arch/x86/include/asm/arch-ivybridge/model_206ax.h | 82 +++
arch/x86/include/asm/arch-ivybridge/pch.h | 356 ++++++++++
arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 ++++
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 109 +++
arch/x86/include/asm/config.h | 1 +
arch/x86/include/asm/global_data.h | 23 +
arch/x86/include/asm/gpio.h | 142 +++-
arch/x86/include/asm/io.h | 49 ++
arch/x86/include/asm/lapic.h | 59 ++
arch/x86/include/asm/lapic_def.h | 101 +++
arch/x86/include/asm/msr.h | 19 +
arch/x86/include/asm/mtrr.h | 121 ++++
arch/x86/include/asm/pci.h | 33 +
arch/x86/include/asm/post.h | 50 ++
arch/x86/include/asm/processor.h | 2 +
arch/x86/include/asm/u-boot-x86.h | 2 +
arch/x86/lib/Makefile | 1 +
arch/x86/lib/ramtest.c | 79 +++
arch/x86/lib/tsc_timer.c | 32 +-
.../{chromebook-x86 => coreboot}/coreboot/Kconfig | 2 +-
.../coreboot/MAINTAINERS | 2 +-
.../{chromebook-x86 => coreboot}/coreboot/Makefile | 0
.../coreboot/coreboot.c | 0
.../coreboot/coreboot_start.S | 0
board/google/chromebook_link/Kconfig | 31 +
board/google/chromebook_link/MAINTAINERS | 6 +
board/google/chromebook_link/Makefile | 15 +
board/google/chromebook_link/link.c | 124 ++++
board/google/common/Makefile | 7 +
board/google/common/early_init.S | 29 +
configs/chromebook_link_defconfig | 10 +
doc/device-tree-bindings/misc/intel-lpc.txt | 23 +
drivers/gpio/intel_ich6_gpio.c | 79 ++-
include/configs/chromebook_link.h | 74 ++
include/configs/x86-common.h | 2 +-
include/fdtdec.h | 2 +
lib/fdtdec.c | 2 +
tools/ifdtool.c | 2 +-
70 files changed, 6079 insertions(+), 109 deletions(-)
create mode 100644 arch/x86/cpu/ivybridge/Kconfig
create mode 100644 arch/x86/cpu/ivybridge/Makefile
create mode 100644 arch/x86/cpu/ivybridge/car.S
create mode 100644 arch/x86/cpu/ivybridge/cpu.c
create mode 100644 arch/x86/cpu/ivybridge/early_init.c
create mode 100644 arch/x86/cpu/ivybridge/early_me.c
create mode 100644 arch/x86/cpu/ivybridge/lpc.c
create mode 100644 arch/x86/cpu/ivybridge/me_status.c
create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c
create mode 100644 arch/x86/cpu/ivybridge/pci.c
create mode 100644 arch/x86/cpu/ivybridge/report_platform.c
create mode 100644 arch/x86/cpu/ivybridge/sdram.c
create mode 100644 arch/x86/cpu/pci.c
create mode 120000 arch/x86/dts/chromebook_link.dts
create mode 100644 arch/x86/dts/m12206a7_00000028.dtsi
create mode 100644 arch/x86/dts/m12306a9_00000017.dtsi
create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/model_206ax.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/pch.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h
create mode 100644 arch/x86/include/asm/lapic.h
create mode 100644 arch/x86/include/asm/lapic_def.h
create mode 100644 arch/x86/include/asm/mtrr.h
create mode 100644 arch/x86/include/asm/post.h
create mode 100644 arch/x86/lib/ramtest.c
rename board/{chromebook-x86 => coreboot}/coreboot/Kconfig (86%)
rename board/{chromebook-x86 => coreboot}/coreboot/MAINTAINERS (78%)
rename board/{chromebook-x86 => coreboot}/coreboot/Makefile (100%)
rename board/{chromebook-x86 => coreboot}/coreboot/coreboot.c (100%)
rename board/{chromebook-x86 => coreboot}/coreboot/coreboot_start.S (100%)
create mode 100644 board/google/chromebook_link/Kconfig
create mode 100644 board/google/chromebook_link/MAINTAINERS
create mode 100644 board/google/chromebook_link/Makefile
create mode 100644 board/google/chromebook_link/link.c
create mode 100644 board/google/common/Makefile
create mode 100644 board/google/common/early_init.S
create mode 100644 configs/chromebook_link_defconfig
create mode 100644 doc/device-tree-bindings/misc/intel-lpc.txt
create mode 100644 include/configs/chromebook_link.h
--
2.1.0.rc2.206.gedb03e5
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