On Friday, August 12, 2011 11:57:08 AM Albert ARIBAUD wrote:
> On 11/08/2011 09:30, Marek Vasut wrote:
> > That's actually not a bad idea, but we need to be definitelly 100% sure
> > it'll work for all these different v5 and v6 cores !
>
> That's what I'm afraid of: not all v5 or v6 cores may have
On 11/08/2011 09:30, Marek Vasut wrote:
> That's actually not a bad idea, but we need to be definitelly 100% sure it'll
> work for all these different v5 and v6 cores !
That's what I'm afraid of: not all v5 or v6 cores may have the same set
of cache functions. I'll have a look at various ARMv5 b
On Thursday, August 11, 2011 09:02:20 AM Aneesh V wrote:
> Hi Albert, Hong,
>
> On Wednesday 10 August 2011 12:06 PM, Albert ARIBAUD wrote:
> > Hi Hong Xu,
> >
> > Le 10/08/2011 08:17, Hong Xu a écrit :
> >> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
> >> put the stuff
Hi Albert, Hong,
On Wednesday 10 August 2011 12:06 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 10/08/2011 08:17, Hong Xu a écrit :
>
>> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
>> put the stuff there. ;-) I think Albert Aribaud or the original
>> contributor of cac
On Wednesday, August 10, 2011 08:41:58 AM Hong Xu wrote:
> Hi Albert,
>
> On 08/10/2011 02:36 PM, Albert ARIBAUD wrote:
> > Hi Hong Xu,
> >
> > Le 10/08/2011 08:17, Hong Xu a écrit :
> >> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
> >> put the stuff there. ;-) I think
Hi Albert,
On 08/10/2011 02:36 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 10/08/2011 08:17, Hong Xu a écrit :
>
>> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
>> put the stuff there. ;-) I think Albert Aribaud or the original
>> contributor of cache part shall have c
Hi Hong Xu,
Le 10/08/2011 08:17, Hong Xu a écrit :
> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
> put the stuff there. ;-) I think Albert Aribaud or the original
> contributor of cache part shall have clearer view.So, I'll keep neutral
> to hear more ideas.
Basically,
Hi Marek Vasut,
On 08/10/2011 01:52 PM, Marek Vasut wrote:
> On Wednesday, August 10, 2011 04:49:25 AM Hong Xu wrote:
>> After DMA operation, we need to maintain D-Cache coherency.
>> So that the DCache must be invalidated (hence CPU will fetch
>> data written by DMA controller from RAM).
>>
>> Te
Hello Hong,
Marek Vasut wrote:
> On Wednesday, August 10, 2011 04:49:25 AM Hong Xu wrote:
>> After DMA operation, we need to maintain D-Cache coherency.
>> So that the DCache must be invalidated (hence CPU will fetch
>> data written by DMA controller from RAM).
>>
>> Tested on AT91SAM9261EK with P
On Wednesday, August 10, 2011 04:49:25 AM Hong Xu wrote:
> After DMA operation, we need to maintain D-Cache coherency.
> So that the DCache must be invalidated (hence CPU will fetch
> data written by DMA controller from RAM).
>
> Tested on AT91SAM9261EK with Peripheral DMA controller.
Hi Hong,
o
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