Hello Hong, Marek Vasut wrote: > On Wednesday, August 10, 2011 04:49:25 AM Hong Xu wrote: >> After DMA operation, we need to maintain D-Cache coherency. >> So that the DCache must be invalidated (hence CPU will fetch >> data written by DMA controller from RAM). >> >> Tested on AT91SAM9261EK with Peripheral DMA controller. > > Hi Hong, > > one more thing, not that I want to disappoint you. > > Try to take a look at arch/arm/cpu/armv7/cache_v7.c > > Maybe we should do the same for arm926ejs -- have > arch/arm/cpu/arm926ejs/cache.c > -- containing arm926ejs specific cache management functions. That way, > arch/arm/lib/cache.c won't become mess. > > What do you think ?
Full Ack, this should be moved like on armv7 to arch/arm/cpu/arm926ejs/cache.c Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
