Dear Prafulla Wadaskar,
In message
you wrote:
>
> 1. ns16550 is standard IP used across several SoC and has driver in place.
> 2. Your specific implementation of the same IP on your specific SoC need
> bit9 or x register to be set to 0 to work this IP correctly on your h/w.
> 3. but doing in ns
> -Original Message-
> From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> On Behalf Of Lei Wen
> Sent: Friday, April 01, 2011 8:04 PM
> To: Wolfgang Denk
> Cc: Lei Wen; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] serial: ns16550: f
Dear Lei Wen,
In message you
wrote:
>
> Just a question to clarify... What your point I denied, that is really
> confused me...
> I think in this thread, I explain to you, my patch could recover what original
> CONFIG_SYS_NS16550_REG_SIZE means...
But there is nothing to "recover" in that dri
Hi Wolfgang,
On Fri, Apr 1, 2011 at 10:25 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message you
> wrote:
>>
>> >> > I don't think so. You still use just a single writel() call then. To
>> >> > leave the other bits untouched, you would have to perform a readl()
>> >> > first, then insert
Dear Lei Wen,
In message you
wrote:
>
> >> > I don't think so. You still use just a single writel() call then. To
> >> > leave the other bits untouched, you would have to perform a readl()
> >> > first, then insert one data byte, and then write it back. Your patch
> >> > does not do that.
> >
Hi Wolfgang,
On Fri, Apr 1, 2011 at 9:55 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message
> you wrote:
>>
>> >> I think my code also could handle this. They only could set the
>> >> CONFIG_SYS_NS16550_REG_SIZE =A0to be 1
>> >> and CONFIG_SYS_NS16550_MAX_REG_SIZE to be 4. Then
>> >> the o
Dear Lei Wen,
In message you
wrote:
>
> >> I think my code also could handle this. They only could set the
> >> CONFIG_SYS_NS16550_REG_SIZE =A0to be 1
> >> and CONFIG_SYS_NS16550_MAX_REG_SIZE to be 4. Then
> >> the other bits is untouched by this driver.
> >
> > I don't think so. You still use j
On Fri, Apr 1, 2011 at 8:41 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message you
> wrote:
>>
>> I think my code also could handle this. They only could set the
>> CONFIG_SYS_NS16550_REG_SIZE to be 1
>> and CONFIG_SYS_NS16550_MAX_REG_SIZE to be 4. Then
>> the other bits is untouched by th
Dear Lei Wen,
In message you
wrote:
>
> I think my code also could handle this. They only could set the
> CONFIG_SYS_NS16550_REG_SIZE to be 1
> and CONFIG_SYS_NS16550_MAX_REG_SIZE to be 4. Then
> the other bits is untouched by this driver.
I don't think so. You still use just a single writel(
Hi Wolfgang,
On Fri, Apr 1, 2011 at 6:25 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message you
> wrote:
>>
>> > 3. You say that the current implementation, which uses a writeb() call
>> > (i. e. a byte write operation) to this register would not only
>> > affect bits 0...7, as expecte
Dear Lei Wen,
In message you
wrote:
>
> > 3. You say that the current implementation, which uses a writeb() call
> > (i. e. a byte write operation) to this register would not only
> > affect bits 0...7, as expected, but also clear bit 9.
>
> That is not my case. In my case, for writeb, it
Hi Wolfgang,
On Fri, Apr 1, 2011 at 3:39 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message you
> wrote:
>>
>> > This makes no sense to me. I have never seen any 9 bit registers in
>> > any processor I ever encountered in real life.
>>
>> I don't mean that register is 9bit...
>> I means th
Dear Lei Wen,
In message you
wrote:
>
> > This makes no sense to me. I have never seen any 9 bit registers in
> > any processor I ever encountered in real life.
>
> I don't mean that register is 9bit...
> I means that register, IER, is 32bit long, but 9-31th bit is reserved, and
> 0th to 8th b
Hi Wolfgang,
On Fri, Apr 1, 2011 at 1:35 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message you
> wrote:
>>
>> > Can you please explain on what board, and with which tool chain, you
>> > see any problems?
>>
>> I test on Marvell pxa955 (MG1) board, with android 4.4.0 toolchain.
>> The pxa9
Dear Lei Wen,
In message you
wrote:
>
> > Can you please explain on what board, and with which tool chain, you
> > see any problems?
>
> I test on Marvell pxa955 (MG1) board, with android 4.4.0 toolchain.
> The pxa955's ns16550 register's IER has nine bits. The 8th bit is HSE, which
> means the
Hi Wolfgang,
On Thu, Mar 31, 2011 at 11:58 PM, Wolfgang Denk wrote:
> Dear Lei Wen,
>
> In message <1301586774-25447-1-git-send-email-lei...@marvell.com> you wrote:
>> Some hardware would dysfunctional if only access the register by
>> byte. This patch is tend to recover original access the respo
Dear Lei Wen,
In message <1301586774-25447-1-git-send-email-lei...@marvell.com> you wrote:
> Some hardware would dysfunctional if only access the register by
> byte. This patch is tend to recover original access the responding
> register according to CONFIG_SYS_NS16550_REG_SIZE.
Can you please ex
Some hardware would dysfunctional if only access the register by
byte. This patch is tend to recover original access the responding
register according to CONFIG_SYS_NS16550_REG_SIZE.
Signed-off-by: Lei Wen
---
README |5
drivers/serial/ns16550.c |7 --
include/
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