Hi Wolfgang, On Thu, Mar 31, 2011 at 11:58 PM, Wolfgang Denk <w...@denx.de> wrote: > Dear Lei Wen, > > In message <1301586774-25447-1-git-send-email-lei...@marvell.com> you wrote: >> Some hardware would dysfunctional if only access the register by >> byte. This patch is tend to recover original access the responding >> register according to CONFIG_SYS_NS16550_REG_SIZE. > > Can you please explain on what board, and with which tool chain, you > see any problems?
I test on Marvell pxa955 (MG1) board, with android 4.4.0 toolchain. The pxa955's ns16550 register's IER has nine bits. The 8th bit is HSE, which means the high speed mode. It seems something wrong there, if access the ier by byte, the 8th bit would be 1 at the beginning, and would be cleared by the following set value in the ns16550 driver, which cause problem on that board, for the baudrate would be dysfunction. If access the ier by int type, then the 8bit would be cleared, and uart behavior normal. > >> +- CONFIG_SYS_NS16550_MAX_REG_SIZE: >> + Define the ns16550 max register size, >> + if the CONFIG_SYS_NS16550_REG_SIZE is smaller than this value, >> + use padding to fill those gap. > > This makes no sense to me. A register is always one specific size, > so the term "MAX_REG_SIZE" is bogus. I introduce this CONFIG is for I found when CONFIG_SYS_NS16550_REG_SIZE is 1 or -1, there would be no prepad in the structure. And this means the register size is char only? Best regards, Lei _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
