> From: Fleming Andy-AFLEMING [aflem...@freescale.com]
> Sent: Saturday, April 06, 2013 00:18
> To: Eric Nelson
> Cc: Gabbasov, Andrew; u-boot@lists.denx.de; Behme, Dirk - Bosch; Estevam
> Fabio-R49496
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA opera
: Gabbasov, Andrew Cc:
u-boot@lists.denx.de; Behme, Dirk - Bosch; Fabio Estevam
Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for
DMA operation completion
So, do you think the latter (modified) loop condition
} while (!(irqstat & IRQSTAT_TC) || !(irqstat & IRQS
Andrew
>>> Cc: u-boot@lists.denx.de; Behme, Dirk - Bosch; Fabio Estevam
>>> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
>>> completion
>>>
>>
>> So, do you think the latter (modified) loop condition
>>
>>
Hi Andrew,
On 04/04/2013 11:03 AM, Gabbasov, Andrew wrote:
Hi Eric,
From: Eric Nelson [eric.nel...@boundarydevices.com]
Sent: Thursday, April 04, 2013 03:47
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de; Behme, Dirk - Bosch; Fabio Estevam
Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix
On Apr 4, 2013, at 13:12, "Fabio Estevam" wrote:
> Hi Eric,
>
> On Wed, Apr 3, 2013 at 8:17 PM, Eric Nelson
> wrote:
>
>>> Actually, I'm a little confused by PRSSTAT_DLA checking: currently the
>>> loop exits
>>> when either IRQSTAT_TC occurs _or_ PRSSTAT_DLA flag comes to 0. Is that
>>> cor
Hi Eric,
On Wed, Apr 3, 2013 at 8:17 PM, Eric Nelson
wrote:
>> Actually, I'm a little confused by PRSSTAT_DLA checking: currently the
>> loop exits
>> when either IRQSTAT_TC occurs _or_ PRSSTAT_DLA flag comes to 0. Is that
>> correct?
>> I'm not quite familiar with using this flag, but should th
Hi Eric,
> From: Eric Nelson [eric.nel...@boundarydevices.com]
> Sent: Thursday, April 04, 2013 03:47
> To: Gabbasov, Andrew
> Cc: u-boot@lists.denx.de; Behme, Dirk - Bosch; Fabio Estevam
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
> comple
On 04/03/2013 04:17 PM, Eric Nelson wrote:
Hi Andrew,
On 04/03/2013 10:30 AM, Gabbasov, Andrew wrote:
I think, it would be useful to have both patches. Although
invalidating cache
(by adding some delay) indirectly helps with waiting for DMA End event,
it is probably worth having explicit DMA
Hi Andrew,
On 04/03/2013 10:30 AM, Gabbasov, Andrew wrote:
I think, it would be useful to have both patches. Although invalidating cache
(by adding some delay) indirectly helps with waiting for DMA End event,
it is probably worth having explicit DMA completion waiting patch too.
I agree whol
> From: Eric Nelson [eric.nel...@boundarydevices.com]
> Sent: Wednesday, April 03, 2013 17:38
> To: Gabbasov, Andrew
> Cc: u-boot@lists.denx.de; Behme, Dirk - Bosch
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
> completion
>
> Hi Andrew,
Hi Andrew,
On 04/02/2013 11:48 PM, Gabbasov, Andrew wrote:
On 04/02/2013 03:04 AM, Andrew Gabbasov wrote:
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
the read data is used for some data verification, thos
> From: Eric Nelson [eric.nel...@boundarydevices.com]
> Sent: Wednesday, April 03, 2013 01:50
> To: Dirk Behme
> Cc: Gabbasov, Andrew; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
> completion
>
> Thanks Dirk,
>
> From: Eric Nelson [eric.nel...@boundarydevices.com]
> Sent: Wednesday, April 03, 2013 01:38
> To: Gabbasov, Andrew
> Cc: u-boot@lists.denx.de; Behme, Dirk - Bosch
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
> completion
>
> Thanks Andre
Thanks Dirk,
On 04/02/2013 11:10 AM, Dirk Behme wrote:
Am 02.04.2013 17:49, schrieb Eric Nelson:
Thanks Andrew,
On 04/02/2013 03:04 AM, Andrew Gabbasov wrote:
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
Thanks Andrew,
On 04/02/2013 11:21 AM, Gabbasov, Andrew wrote:
From: Eric Nelson [eric.nel...@boundarydevices.com]
Sent: Tuesday, April 02, 2013 19:49
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
completion
Thanks
> From: Eric Nelson [eric.nel...@boundarydevices.com]
> Sent: Tuesday, April 02, 2013 19:49
> To: Gabbasov, Andrew
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for DMA operation
> completion
>
> Thanks Andrew,
>
> On 04/02/
Am 02.04.2013 17:49, schrieb Eric Nelson:
Thanks Andrew,
On 04/02/2013 03:04 AM, Andrew Gabbasov wrote:
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
the read data is used for some data verification, those o
Thanks Andrew,
On 04/02/2013 03:04 AM, Andrew Gabbasov wrote:
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
the read data is used for some data verification, those obtained data
may be incomplete, which cause
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
the read data is used for some data verification, those obtained data
may be incomplete, which causes intermittent verification failures.
For example, when the defa
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