Thanks for the review Andy.
On 04/05/2013 01:18 PM, Fleming Andy-AFLEMING wrote:
On Apr 4, 2013, at 1:41 PM, Eric Nelson wrote:
Hi Andrew,
On 04/04/2013 11:03 AM, Gabbasov, Andrew wrote:
Hi Eric,
From: Eric Nelson [eric.nel...@boundarydevices.com] Sent:
Thursday, April 04, 2013 03:47 To: Gabbasov, Andrew Cc:
u-boot@lists.denx.de; Behme, Dirk - Bosch; Fabio Estevam
Subject: Re: [U-Boot] [PATCH] mx6: fsl_esdhc: Fix waiting for
DMA operation completion
So, do you think the latter (modified) loop condition
} while (!(irqstat & IRQSTAT_TC) || !(irqstat & IRQSTAT_DINT) ||
(esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
will be correct?
I think the right thing to do is eliminate the DLA test entirely,
so the loop condition can be simplified to something like this:
#define TRANSFER_COMPLETE (IRQSTAT_TC|IRQSTAT_DINT)
do { ... } while (TRANSFER_COMPLETE !=
(irqstat&TRANSFER_COMPLETE));
That looks right to me. I have been known to mistakenly write loops
that are supposed to wait for two conditions to only wait for one of
those. Apparently I need remedial boolean logic lessons.
If there is another part that needs to bail out on PRSSTAT_DLA, it
seems that the affected part should be the one with the #ifdef
I don't think we need a special case. Just correct logic. :/
Cool. It's always hard to tell when IP like this is used for
multiple processors.
So many data sheets, so little time...
Regards,
Eric
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