> From: Heinrich Schuchardt
> Sent: Saturday, September 23, 2023 7:35 AM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
>
> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
>
> Subject: [PATCH 1/1] riscv: enable CONFIG_DEBUG_UART by default
>
> Most boards d
> From: Tom Rini
> Sent: Friday, October 13, 2023 7:04 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
>
> Subject: [PATCH 7/7] riscv: Remove common.h usage
>
> We can remove common.h from most cases of the code here, and only
> From: Heinrich Schuchardt
> Sent: Sunday, October 01, 2023 1:41 PM
> To: Paul Walmsley ; Green Wan
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; u-boot@lists.denx.de; Heinrich Schuchardt
>
> Subject: [PATCH 1/1] configs: sifive: enable poweroff command on U
> Hi Rick,
>
> On Wed, 19 Apr 2023 at 00:56, Rick Chen wrote:
> >
> > Hi Simon,
> >
> > > Hi Rick,
> > >
> > > On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> > > >
> > > > Allow U-Boot to load 32 or 64 bits RIS
> From: Heinrich Schuchardt
> Sent: Wednesday, July 26, 2023 2:05 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: Leo Yu-Chi Liang(梁育齊) ; u-boot@lists.denx.de;
> Heinrich Schuchardt
> Subject: [PATCH v2 1/1] acpi: Add missing RISC-V acpi_table header
>
> The pci_mmc.c driver ca
> From: Heinrich Schuchardt
> Sent: Tuesday, July 25, 2023 6:42 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
>
> Cc: Paul Walmsley ; Green Wan
> ; u-boot@lists.denx.de; Heinrich Schuchardt
>
> Subject: [PATCH 1/1] riscv: sifive: initialize PCI on Unmatched
e/configs/qemu-riscv.h| 2 +-
> 4 files changed, 16 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
tion/qemu-riscv/qemu-riscv.c | 24
> include/configs/qemu-riscv.h| 10 --
> 2 files changed, 34 deletions(-)
Reviewed-by: Rick Chen
on/qemu-riscv/Kconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Rick Chen
> From: Bin Meng
> Sent: Wednesday, June 21, 2023 11:07 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
>
> In
> From: Bin Meng
> Sent: Wednesday, June 21, 2023 11:12 PM
> To: u-boot@lists.denx.de
> Cc: Anup Patel ; Atish Patra ;
> Bin Meng ; Palmer Dabbelt ; Paul
> Walmsley ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH v2 1/3] riscv: timer: Update the sifive clint timer dri
> From: Yanhong Wang
> Sent: Thursday, June 15, 2023 5:37 PM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) ; Leo
> Yu-Chi Liang(梁育齊) ; Joe Hershberger
> ; Ramon Fried
> Cc: Yanhong Wang ; Torsten Duwe ;
> Leyfoon Tan ; samin . guo
> ; Walker Chen ; Hal
> Fe
> From: Yanhong Wang
> Sent: Thursday, June 15, 2023 5:37 PM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) ; Leo
> Yu-Chi Liang(梁育齊) ; Joe Hershberger
> ; Ramon Fried
> Cc: Yanhong Wang ; Torsten Duwe ;
> Leyfoon Tan ; samin . guo
> ; Walker Chen ; Hal
> Fe
> From: Conor Dooley
> Sent: Thursday, June 15, 2023 6:13 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Padmarao Begari ;
> Conor Dooley
> Subject: [PATCH v2 2/3] riscv: dts: sync mpfs-icicle devicetree with linux
>
> The &
> From: Bin Meng
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Andre Przywara ; Anup Patel
> ; Jonas Schwöbel ; Kautuk
> Consul ; Leo Yu-Chi Liang(梁育齊)
> ; Michael Walle ; Michal Simek
> ; Nikita Shubin ; Rick Jian-Zhi
> Chen(陳建志) ; Sean A
> > From: Bin Meng
> > Sent: Monday, June 12, 2023 3:36 PM
> > To: u-boot@lists.denx.de
> > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> >
> > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to
> > support aclint
&
> From: Bin Meng
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to
> support aclint
>
> This RISC-V ACLINT specification
Hi Bin,
> From: Bin Meng
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Anup Patel ; Atish Patra ;
> Bin Meng ; Palmer Dabbelt ; Paul
> Walmsley ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer dri
> From: Conor Dooley
> Sent: Wednesday, June 07, 2023 6:06 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Padmarao Begari ;
> Conor Dooley
> Subject: [PATCH v1 1/3] riscv: dts: drop microchip from dts filenames
>
> The origi
> From: Bo Gan
> Sent: Monday, June 12, 2023 7:59 AM
> To: u-boot@lists.denx.de
> Cc: Bo Gan ; samin . guo ;
> Yanhong Wang ; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ; Sean
> Anderson ; Lukasz Majewski
> Subject: [RESEND PATCH v1] arch: riscv: jh711
> From: Bo Gan
> Sent: Monday, June 12, 2023 7:54 AM
> To: u-boot@lists.denx.de
> Cc: Bo Gan ; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ; Sean
> Anderson ; Bin Meng ; Lukas Auer
>
> Subject: [RESEND PATCH v2] riscv: setup per-hart stack earlier
>
> Ha
Hi Minda
> From: Minda Chen
> Sent: Thursday, June 01, 2023 9:07 AM
> To: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Simon Glass ; Stefan Roese
> ; Andrew Scull ; Pali Rohár
> ; Mark Kettenis
> Cc: u-boot@lists.denx.de; Mason Huo ; Leyfoon Tan
> ; Kevin Xi
Hi Bo Gan,
> From: Bo Gan
> Sent: Tuesday, May 09, 2023 9:46 AM
> To: u-boot@lists.denx.de
> Cc: Bo Gan ; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊)
> Subject: [PATCH] riscv: setup per-hart stack earlier
>
> Harts need to use per-hart stack before any fun
Hi Simon,
> Hi Rick,
>
> On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> >
> > Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
> > distinguishly. It helps to avoid someone maybe make a mistake
> > to run 32-bit U-Boot to load 64-bit kernel.
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH 7/8] riscv: spl: Remove relocation sections
>
> U-Boot SPL is not reloc
Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
distinguishly. It helps to avoid someone maybe make a mistake
to run 32-bit U-Boot to load 64-bit kernel.
Signed-off-by: Rick Chen
---
The patchset is based on Simon's patch:
riscv: Add a 64-bit image type
---
---
arch/riscv/include/
> From: Simon Glass
> Sent: Monday, April 03, 2023 4:28 AM
> To: U-Boot Mailing List
> Cc: Sean Anderson ; Bin Meng ; Rick
> Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Simon Glass ; Andre Przywara
> ; Marc Kleine-Budde ; SESA644425
> ; Samuel Holland ; Steve
rgument of prelink-riscv
>
> The argv[2] is never used in prelink-riscv. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH 4/8] tools: prelink-riscv: Unmap the ELF image when done
>
> The codes forget to call munmap() to unmap the E
v.inc | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Nikita Shubin
> ; Rick Jian-Zhi Chen(陳建志)
> Subject: [PATCH 2/8] riscv: Optimize loading relocation type
>
> 't5' already contains relocation
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Nikita Shubin
> ; Rick Jian-Zhi Chen(陳建志)
> Subject: [PATCH 1/8] riscv: Optimize source end address calculation in start.S
>
> The __bss_start is the sourc
> From: Bin Meng
> Sent: Monday, April 03, 2023 11:38 AM
> To: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
>
> Cc: u-boot@lists.denx.de
> Subject: [PATCH] riscv: Correct a comment in io.h
>
> Replace NDS32 with RISC-V in the comments.
>
> Signed-off-by: B
0
> Out: serial@13140
> Err: serial@13140
> Model: test,test
> Net: No ethernet found.
> Hit any key to stop autoboot: 0
> Moving Image from 0x400600 to 0x400020, end=4000b01c8c ## Flattened
> Device Tree blob at ff76a1d0
>Booting using the fdt blob at 0xff76a1d0
> ERROR: Failed to allocate 0x100 bytes below 0x1.
Can you dig in where to print this ERROR ?
Thanks,
Rick
> ramdisk - allocation error
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
Changes in v2
- Add more descriptions about fw_dynamic.bin
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 6 ++
2 fil
Hi Leo
> On Thu, Feb 16, 2023 at 09:19:45AM +0800, Rick Chen wrote:
> > Add the 'missing-msg' for more detailed output
> > on missing system firmware.
> >
> > Signed-off-by: Rick Chen
> > ---
> > arch/riscv/dts/binman.dtsi | 1 +
> >
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Tuesday, February 14, 2023 6:19 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; s...@chromium.org; xypron.g...@gmx.de; Peter Yu-Chien
> Lin(林宇謙) ; Samuel Holland
> Subject: [RFC PATCH v3] do
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 4
2 files changed, 5 insertions(+)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.
> From: Leo Yu-Chi Liang(梁育齊)
> Sent: Thursday, February 09, 2023 4:34 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Peter Yu-Chien Lin(林宇謙)
> ; Leo Yu-Chi Liang(梁育齊)
> Subject: [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
>
> Signed-
> From: Leo Yu-Chi Liang(梁育齊)
> Sent: Thursday, February 09, 2023 4:34 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Peter Yu-Chien Lin(林宇謙)
> ; Leo Yu-Chi Liang(梁育齊)
> Subject: [PATCH 1/2] riscv: Rename Andes cpu and board names
>
> The current ae350-
s with read and write callbacks to allow the 'mii'
> command to work. Use a timeout of 10 ms to wait for the R/W operations to
> complete.
>
> Signed-off-by: Sergei Antonov
> ---
Reviewed-by: Rick Chen
Tested-by: Rick Chen
I have verified this patch on AE350 platform an
#x27;phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in struct
> ftmac100_data. It allows to remove casting in a number of places.
>
> Since priv->iobase is phys_addr_t, use phys_to_virt() to make a pointer from
> it.
>
> Signed-off-by: Sergei Antonov
Reviewed-by: Rick Chen
> So it will be named similarly to the related ftgmac100 driver.
> The old name 'nds32_mac' is not referred to anywhere in U-Boot.
>
> Signed-off-by: Sergei Antonov
> Reviewed-by: Ramon Fried
Reviewed-by: Rick Chen
Hi Zong,
> From: Leo Yu-Chi Liang(梁育齊)
> Sent: Monday, February 06, 2023 3:58 PM
> To: Simon Glass
> Cc: U-Boot Mailing List ; Rick Jian-Zhi Chen(陳建志)
> ; zong...@sifive.com; vincent.c...@sifive.com
> Subject: Re: Docs for RISC-V
>
> Hi Simon,
>
> On Thu, Fe
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 09/10] configs: ae350: Display C
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 07/10] configs: ae350: Enable
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 06/10] riscv: ax25: cache.c: Cl
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 05/10] riscv: ae350: dts: Update L2 ca
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 04/10] riscv: cpu: ax25: Simplify ca
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 03/10] driver: cache: cache-v5l2:
Hi Peter,
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms
>
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in
> spl_bo
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 02/11] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW
>
> P
> On Wed, Jan 4, 2023 at 10:08 AM Rick Chen wrote:
> >
> > Original openSBI (without FW_PIC) will relocate itself
>
> nits: OpenSBI
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
>
> ditto
OK, will fix it.
>
> > it will not
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
Reviewed-by: Bin Meng
---
Changes in v4
- fix openSBI typo
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 inser
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
---
Changes in v3
- fix typos
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Add src and dst address checking, if they
are the same address, just return and don't
copy data anymore.
Signed-off-by: Rick Chen
---
Changes in v3
- new patch: separate from [1/2]
---
arch/riscv/lib/memcpy.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b
declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.
Signed-off-by: Rick Chen
---
Changes in v3
- fix aligment
- refine board_spl_fit_buffer_addr
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu
> Hi Rick,
>
> On 1/3/23 02:20, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > memory address and copy whole fit image to this
Hi Samuel
> On 1/3/23 02:18, Rick Chen wrote:
> > Original openSBI (without FW_PIC) will relocate itselt
>
> typo: itself
OK, I will fix it.
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
> > it will not relocate any more and alaways run at 0x10
d-off-by: Rick Chen
---
Changes in v2
- Move spl.c to board level instead of arch level
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu/ax25/spl.c| 31 +++
arch/riscv/lib/memcpy.S | 2 ++
3 files changed, 34 insertions(+)
create mode 100644 arch/risc
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- describe why is this change a must have
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+),
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- correct aligment
---
arch/riscv/cpu/ax25/cpu.c | 18
> On 12/27/22 21:22, Rick Chen wrote:
> > Hi Samuel,
> >
> > Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
> >>
> >> On 12/22/22 01:21, Rick Chen wrote:
> >>> When fit image boots from ram, the payload will
> >>> be prepared in the add
Hi Samuel,
Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
>
> On 12/22/22 01:21, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > mem
> On Thu, Dec 22, 2022 at 4:07 PM Rick Chen wrote:
> >
> > > On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> > &
> On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> > > >
> > > > Change openSBI load address from 0x100 to 0x0 and it
> > >
> > > nits: Ope
d-off-by: Rick Chen
---
arch/riscv/lib/memcpy.S | 2 ++
arch/riscv/lib/spl.c| 16
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 00672c19ad..9884077c93 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/mem
> From: Yanhong Wang
> Sent: Monday, December 12, 2022 10:50 AM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) ; Leo
> Yu-Chi Liang(梁育齊) ; Lukasz Majewski ;
> Sean Anderson
> Cc: Lee Kuan Lim ; Jianlong Huang
> ; Emil Renner Berthing ;
> Yanhong Wang
> Subj
Hi Bin,
> On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> >
> > Change openSBI load address from 0x100 to 0x0 and it
>
> nits: OpenSBI
OK, will fix it.
>
> > will start to run at 0x0 directly without relocation.
> >
> > Signed-off-by: Rick Che
Hi Bin
> On Wed, Dec 21, 2022 at 11:00 AM Rick Chen wrote:
> >
> > CCTL operations are available to Supervisor/User-mode
> > software under the control of the mcache_ctl.CCTL_SUEN
> > control bit. Enable it to support Superviosr(and User)
>
> typo: Supervi
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Superviosr(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
arch/riscv/cpu/ax25/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a
Change openSBI load address from 0x100 to 0x0 and it
will start to run at 0x0 directly without relocation.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board
> On 12/13/22 11:24, Tom Rini wrote:
> > On Tue, Dec 13, 2022 at 08:42:47AM +0800, Rick Chen wrote:
> >> Hi Sean,
> >>
> >>> On 12/12/22 10:03, Tom Rini wrote:
> >>>> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >>>&
Hi Tom,
> On Wed, Dec 14, 2022 at 08:49:03AM +0800, Rick Chen wrote:
> > Hi Tom,
> >
> > > On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > > > On 1
Hi Tom,
> On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > > In RISC-V, it only provide normal mode booting currently
> On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > On 12/7/22 01:23, Rick Chen wrote:
> > > > In RISC-V, it only provide normal mode booting currently.
> > > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > >
Hi Tom
> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > In RISC-V, it only provide normal mode b
Hi Sean,
> On 12/12/22 10:03, Tom Rini wrote:
> > On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >> Hi Tom
> >>
> >>> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> >>>> On 12/7/22 01:23, Rick Chen wrote:
> On 12/7/22 01:23, Rick Chen wrote:
> > In RISC-V, it only provide normal mode booting currently.
> > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > to achieve this feature which will be call Fast-Boot mode. By
>
> Can you name this something
Hi Tom
> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > On 12/7/22 01:23, Rick Chen wrote:
> > > In RISC-V, it only provide normal mode booting currently.
> > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > to ach
Descript how to boot Kernel with Fast Boot and record
booting messages here.
Signed-off-by: Rick Chen
---
doc/board/AndesTech/ax25-ae350.rst | 140 +
1 file changed, 140 insertions(+)
diff --git a/doc/board/AndesTech/ax25-ae350.rst
b/doc/board/AndesTech/ax25-ae350
Add defconfig for Fast Boot
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 7 ++-
configs/ae350_rv32_spl_fastboot_defconfig | 53 +++
configs/ae350_rv64_spl_fastboot_defconfig | 53 +++
3 files changed, 111 insertions(+), 2
By enabling SPL_OPENSBI_OS_BOOT, it will generate linux.itb instead
of default u-boot.itb after compiling. And Lnux Kernel Image will be
appended in linux.itb. Then it can jump to Linux Kernel from openSBI
directly.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 24
.
Signed-off-by: Rick Chen
---
common/spl/Kconfig | 14 ++
common/spl/spl_fit.c | 3 ++-
common/spl/spl_opensbi.c | 25 -
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 05181bdba3
> From: Zong Li
> Sent: Tuesday, November 29, 2022 10:02 AM
> To: Sean Anderson
> Cc: s...@chromium.org; michal.si...@amd.com; sean.ander...@seco.com; Leo
> Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] riscv: use imply
> From: Zong Li
> Sent: Wednesday, November 16, 2022 3:09 PM
> To: s...@chromium.org; michal.si...@amd.com; sean.ander...@seco.com; Leo
> Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Cc: Zong Li
> Subject: [PATCH] riscv: use imply
> From: Heinrich Schuchardt
> Sent: Tuesday, November 08, 2022 11:14 PM
> To: Bin Meng
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Conor Dooley ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] riscv: clarify meaning of CONFIG_SBI_V02
>
> On 11
Hi Heinrich
> From: Heinrich Schuchardt
> Sent: Tuesday, November 08, 2022 11:14 PM
> To: Bin Meng
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Conor Dooley ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] riscv: clarify meaning of CONFIG_SBI_V02
>
>
.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/cpu.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Tuesday, October 25, 2022 11:04 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH] riscv: Rename Andes PLIC to PLICSW
>
> As PLICSW is used to trigge
> From: Padmarao Begari
> Sent: Thursday, October 27, 2022 2:02 PM
> To: u-boot@lists.denx.de; ja...@amarulasolutions.com; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ;
> bmeng...@gmail.com
> Cc: cyril.j...@microchip.com; conor.doo...@microchip.com;
> v
> From: Padmarao Begari
> Sent: Thursday, October 27, 2022 2:02 PM
> To: u-boot@lists.denx.de; ja...@amarulasolutions.com; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ;
> bmeng...@gmail.com
> Cc: cyril.j...@microchip.com; conor.doo...@microchip.com;
> v
> From: Padmarao Begari
> Sent: Thursday, October 27, 2022 2:02 PM
> To: u-boot@lists.denx.de; ja...@amarulasolutions.com; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ;
> bmeng...@gmail.com
> Cc: cyril.j...@microchip.com; conor.doo...@microchip.com;
> v
Check firmware_fdt_addr header to see if it
is a valid fdt blob.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Friday, October 14, 2022 3:00 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH] riscv: andes_plic.c: use modified IPI scheme
>
> The IPI scheme in Ope
> From: Bin Meng
> Sent: Monday, October 17, 2022 12:42 AM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; u-boot@lists.denx.de
> Cc: fal...@tinylab.org; Yangjie Zhang
> Subject: [PATCH] riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+
>
> Since Ope
Check firmware_fdt_addr header to see if it is a valid
fdt blob.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index
HI Heinrich
> >> From: Heinrich Schuchardt
> >> Sent: Saturday, October 08, 2022 5:18 PM
> >> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> >>
> >> Cc: Tom Rini ; u-boot@lists.denx.de; Heinrich
> >> Schuchardt
> >> Su
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