On Sun, Aug 03, 2025 at 09:21:23AM +0800, Yixun Lan wrote:
> Hi Yao,
>
> On 09:21 Sat 02 Aug , Yao Zi wrote:
> > Add an alternative implementation that use Zalrsc extension only for
> > HART lottery and SMP locking to support SMP on cores without "Zaamo"
>
On Sun, Aug 03, 2025 at 09:24:22AM +0800, Yixun Lan wrote:
> Hi Yao,
>
> On 09:21 Sat 02 Aug , Yao Zi wrote:
> > Ratified on Apr. 2024, the original RISC-V "A" extension is now split
> > into two separate extensions, "Zaamo" for atomic operations
On Sun, Aug 03, 2025 at 07:59:05AM +0800, Yixun Lan wrote:
> Hi Yao,
>
> On 09:21 Sat 02 Aug , Yao Zi wrote:
> > Ratified on Apr. 2024, the original RISC-V "A" extension is now split
> > into two separate extensions, "Zaamo" for atomic operations
Add an alternative implementation that use Zalrsc extension only for
HART lottery and SMP locking to support SMP on cores without "Zaamo"
extension available. The Zaamo implementation is still used by default
since since the Zalrsc one requires more instructions.
Signed-off-by: Yao Zi
matically generate atomic
instructions unless the source explicitly instructs it to do so, thus
this should be safe.
Link:
https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126
# [1]
Link:
https://lore.kernel.org/u-boot/20250729162035.209849-9-ur
ethernet found.
without this series, U-Boot won't run if Zaamo is disabled with
-cpu rv64,zaamo=off.
Yao Zi (2):
riscv: Add Kconfig options to distinguish Zaamo and Zalrsc
riscv: Add a Zalrsc-only alternative for synchronization in start.S
arch/riscv/Kconfig | 17 +
+static int eg20t_gpio_set_value(struct udevice *dev, unsigned int offset,
> + int value)
> +{
> + struct eg20t_gpio_priv *priv = dev_get_priv(dev);
> + u32 po;
> +
> + po = readl(priv->base + REG_PO);
> + if (value)
> +
value), "r"(mem));
> +}
> +
> +static inline void __arch_putl(unsigned int value, volatile void __iomem
> *mem)
> +{
> + asm volatile("sw %0,0(%1)"::"r"(value), "r"(mem));
> +}
> +
> +static inline void __arch_putq(unsigned int v
Kconfig entry (maybe CONFIG_ISA_ZAMMO) to
represent the availability of Zammo extension. We could use the
alternative path for RISC-V platforms that don't implement Zammo and
disable CONFIG_ISA_ZAAMO, which saves a lot of lines and make the code
cleaner.
Regards,
Yao Zi
> Signed-off-b
CSR in hardware, I suggest
using riscv_aclint_timer.c if the provider of P8700_TIMER is
compatible with the RISC-V ACLINT specification, or just introducing a
new driver otherwise.
Regards,
Yao Zi
> __maybe_unused u32 hi, lo;
>
> if (IS_ENABLED(CONFIG_64BIT))
> --
> 2.34.1
. OK
> + In:serial@d4017000
> + Out: serial@d4017000
> + Err: serial@d4017000
> + Net: No ethernet found.
> + => cpu list
> + 0: cpu@0 spacemit,x60
> + 1: cpu@1 spacemit,x60
> + 2: cpu@2 spacemit,x60
> + 3: cpu@3 spacemit,x60
> + 4: cpu@4 spacemit,x60
> + 5: cpu@5 spacemit,x60
> + 6: cpu@6 spacemit,x60
> + 7: cpu@7 spacemit,x60
> + =>
> \ No newline at end of file
Please restore the EOL :)
Regards,
Yao Zi
[1]:
https://lore.kernel.org/u-boot/20250717024426.26953-1-semen.protse...@linaro.org/
emoved as well for consistency.
Fixes: 5f520875bdf ("kbuild: Bump the build system to 5.1")
Signed-off-by: Yao Zi
Reviewed-by: Ilias Apalodimas
---
Changes from v1
- Don't describe the problem as RISC-V-specific since it may affect ARM
builds as well.
- Prevent config targets
On Fri, Jul 11, 2025 at 08:11:03AM +0300, Ilias Apalodimas wrote:
> Hi Yao,
>
>
> On Wed, 9 Jul 2025 at 19:15, Yao Zi wrote:
> >
> > Stranges errors are observed when building U-Boot master for almost any
> > RISC-V board, the messages are in two types, one i
//gitlab.alpinelinux.org/alpine/aports/-/issues";
$ cat /etc/apk/repositories
#/media/sdb/apks
http://mirrors.ustc.edu.cn/alpine/edge/main
http://mirrors.ustc.edu.cn/alpine/edge/community
http://mirrors.ustc.edu.cn/alpine/edge/testing
This seems to have something to do with the RISC-V failures I tried to
fix days earlier[1], cherry-picking the patch also fixes this failure.
> --
> Tom
Regards,
Yao Zi
[1]: https://lore.kernel.org/u-boot/20250709161418.21287-2-zi...@disroot.org/
#size-cells = <1>;
> + model = "p8700";
> + compatible = "img,boston";
> +
> + chosen {
> + stdout-path = &uart0;
> + bootargs = "root=/dev/sda rw earlycon console=ttyS0,115200n8r";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <2000>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "riscv";
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
riscv,isa is already deprecated in devicetree-binding upstream, it'll
be nice if you could provide a riscv,isa-extensions property as well.
> + status = "okay";
> + reg = <0>;
> + clocks = <&clk_boston BOSTON_CLK_CPU>;
> + clock-frequency = <2000>;
> + bootph-all;
These properties should be sorted, compatible goes first, then reg, and
status should be the last property[1]. This should apply for other nodes
as well.
> + };
> + };
Regards,
Yao Zi
Enable the network stack, the designware ethernet driver and
corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F
phys, both attached to GMAC 0, thus support for Realtek phys and DM
support for MDIO devices are enabled as well.
Signed-off-by: Yao Zi
---
configs
TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 119
arch/riscv/dts/th1520
The Designware IP integrated in TH1520 SoC requires extra clock
configuration to operate correctly. The Linux kernel's T-Head DWMAC glue
driver is ported and adapted to U-Boot's API.
Signed-off-by: Yao Zi
---
MAINTAINERS | 1 +
drivers/net/Kconfig | 8 ++
d
TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/dram.c
flags, and pass it to
divider_recalc_rate(). With this fix, frequency of all the clocks match
the Linux kernel's calculation.
Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC")
Signed-off-by: Yao Zi
---
drivers/clk/thead/clk-th1520-ap.c | 4 +++-
1 file c
and 1Gbps. Under 1Gbps, tftp could transfer data at
more than 10MiB/s.
Note the bug fixed by the first patch doesn't cause any problem with
existing supported peripherals, thus the fix isn't urgent.
Yao Zi (5):
clk: thead: th1520-ap: Correctly handle flags for dividers
riscv: c
rs since there are no source files
directly under arch/*/cpu, thus the extra include doesn't hurt.
Fixes: 5f520875bdf ("kbuild: Bump the build system to 5.1")
Signed-off-by: Yao Zi
---
I was surprised to see this morning's CI passed[1] even for these RISC-V
boards. Builds
d *blob, int node_offset, phys_addr_t *cpu,
> dma_addr_t *bus, u64 *size);
Regards,
Yao Zi
> This issue was found with Smatch.
>
> Signed-off-by: Andrew Goodbody
> ---
> boot/fdt_support.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/Kconfig | 1 +
configs/th1520_lpi4a_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/cpu
configure are specfied as strings and looked up at runtime, which the
generic pinctrl helpers of U-Boot cannot parse, thus a customized
set_state() callback is implemented to parse pinconfig nodes and setup
the configuration.
Signed-off-by: Yao Zi
---
MAINTAINERS | 1 +
drivers
Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520.dtsi | 28
1
s
on Lichee Pi 4A"[1] for a clean apply. An output of pinmux status -a
could be obtained here[2].
[1]: https://lore.kernel.org/u-boot/20250606042804.64311-1-zi...@disroot.org/
[2]: https://gist.github.com/ziyao233/55738ed1a33d450ccb1dc3752494a2b4
Yao Zi (3):
pinctrl: Port pin controller dri
-riscv/-/pipelines/26483
> >
> > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> > - driver: Add SD card support to the Beagle-V-Fire
>
Setup core information and bring secondary HARTs up for a functional
multi-core system.
Signed-off-by: Yao Zi
---
board/thead/th1520_lpi4a/spl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c
index 25dfa387c36..d75fa6f3eff
Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index 28107a9f354..e773d2e6a80
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/cpu.c
.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/spl.c | 83 +
1 file changed, 83 insertions(+)
diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
index 362fe895f86..b95470485f6 100644
--- a/arch/riscv/cpu/th1520/spl.c
+++ b/arch/riscv/cpu
nt_timer device could be found on IPI initialization.
Signed-off-by: Yao Zi
---
arch/riscv/lib/aclint_ipi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c
index dcd7e5e6b34..1c9a2d70301 100644
--- a/arch/riscv/lib/aclint_ipi.c
+
[1]: https://lore.kernel.org/all/20250530094851.57198-1-zi...@disroot.org/
Yao Zi (5):
riscv: aclint_ipi: Support T-Head C900 CLINT
riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
riscv: cpu: th1520: Add a routine to bring up secondary cores
riscv: dts: th1520: Preserve CLINT node for S
> > and argv.
> >
> > Not sure whether accessing the bootm_headers and gd variables in lib/elf.c
> > is allowed or safe.
> So this is why I was asking if there's some more generalized
> specification we can reference. Is the OS you're using something
> pre-existing and so we need to do what it already expect from some other
> loader? Or is it something you're also creating and if so, why not
> follow the linux kernel convention for compatibility?
>
> --
> Tom
Regards,
Yao Zi
ate a menu entry for these drivers.
Fixes: 6c51df6859f ("dm: Add support for RAM drivers")
Signed-off-by: Yao Zi
---
drivers/ram/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 39d03e8d3d3..edb8e254d5b 100644
--- a/drivers/ra
On Fri, May 30, 2025 at 08:05:48AM -0600, Tom Rini wrote:
> Keep spelling.txt in sync with the version from kernel v6.15.
>
> Reported-by: Yao Zi
> Signed-off-by: Tom Rini
> ---
> Cc: Heinrich Schuchardt
>
> Heinrich, adding 'volatge' here makes sense, but
Add an OpenSBI entry to the FIT image. As it expects an FDT to be
passed, corresponding FDT entry is generated with of-list as well.
As SPL now passes a full FDT for following stages, proper U-Boot image
is packed into u-boot-with-spl.bin without a devicetree copy included.
Signed-off-by: Yao Zi
Assign myself to develop U-Boot port of T-Head TH1520 SoC, and help
maintain related code and review patches.
Signed-off-by: Yao Zi
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d62dd35a385..4d79fa457c4 100644
--- a/MAINTAINERS
+++ b
spelling.txt: remove 'thead' as a typo").
Link: https://www.t-head.cn/ # [1]
Link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=15571273db93ac2e4415e74280e04566c31d5eb0
# [2]
Signed-off-by: Yao Zi
---
scripts/spelling.txt | 1 -
1 file changed,
RISC-V software usually expects S mode when leaving the firmware, e.g.
UEFI applications could only run in S mode. Let's convert proper U-Boot
of Lichee Pi 4A port to run in S mode.
Signed-off-by: Yao Zi
---
configs/th1520_lpi4a_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --
build steps
to mention OpenSBI firmware.
Signed-off-by: Yao Zi
---
doc/board/thead/lpi4a.rst | 125 +++---
1 file changed, 36 insertions(+), 89 deletions(-)
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst
index 7e4c4ea81ee..acd7ac2698d 100644
These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.
Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/cache.c | 2 ++
1 file changed, 2 insertion
Symbols in spl.c only function correctly in SPL stage. Build the file
for SPL only to avoid weak symbols in proper U-Boot being unexpectedly
reloaded.
Fixes: 5fe9ced3552 ("riscv: cpu: Add TH1520 CPU support")
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/Makefile | 2 +-
1 file
consider it's acceptable.
Yao Zi (5):
riscv: cpu: th1520: Build spl.c for SPL only
riscv: cpu: th1520: Support cache enabling/disabling in M mode only
riscv: dts: th1520: Prepare binman configuration for loading OpenSBI
board: thead: licheepi4a: Run proper U-Boot in S-Mode
doc: thead:
t; I'll consider IH_ARCH_RISCV32 a better idea, instead of implying 32bit
> when no suffix attached. We (and the Linux kernel) mix 32-bit and 64-bit
> variants of RISC-V together, thus it's hard to tell the exact bitwidth
> of "IH_ARCH_RISCV" without inspecting the code around. To me, it sounds
> more like "RISC-V, but no bitwidth specified".
>
> It will be nice if we could avoid this kind of ambiguity.
(referring my own reply[1])
I'll second explicit 32-bit and 64-bit entries, and keeping
IH_ARCH_RISCV for compatibility consideration.
>
> Hopefully my lack of bisection isn't causing me to blame something
> incorrect, but I'll go try to replicate now :)
Regards,
Yao Zi
[1]: https://lore.kernel.org/u-boot/z_cjtyxavrpuo...@pie.lan/
The clock driver is essential for TH1520 SoCs to operate. Select the
driver in SoC Kconfig entry.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
index a916d364e6c
Describe the newly-supported clock controller of TH1520 in SoC
devicetree, replace dummy clocks with the controller-supplied ones and
add correct clocks for GPIO controllers.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 8 ---
arch/riscv/dts/th1520.dtsi
igned-off-by: Yao Zi
---
drivers/clk/Kconfig |1 +
drivers/clk/Makefile |1 +
drivers/clk/thead/Kconfig | 19 +
drivers/clk/thead/Makefile|5 +
drivers/clk/thead/clk-th1520-ap.c | 1031 +
5 files changed,
TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
They must be configured before accessing the peripherals. Let's
initialize them in SPL harts_early_init().
Signed-off-by: Yao Zi
---
arch/riscv/cpu/th1520/spl.c| 65 ++
arch/riscv/in
ld be obtained here[2].
Thanks for your time and review.
[1]: https://lore.kernel.org/all/20250513090503.46670-1-zi...@disroot.org/
[2]: https://gist.github.com/ziyao233/75ff1e5b2cf9161093fcc12ed0a62395
Yao Zi (4):
riscv: cpu: th1520: Initialize IOPMPs in SPL
clk: thead: Port clock controller driv
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/dts/th1520.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A
port. Update the documentation of support status and build
instructions.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
doc/board/thead/lpi4a.rst | 58 +--
1 file changed, 55
Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi
Add binman configuration for TH1520 SoC, whose BROM loads the image
combined into SRAM and directly jumps to it. The configuration creates
u-boot-with-spl.bin where the SPL code locates at the start and the DDR
firmware is shipped.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
arch
Memory node is necessary for TH1520 SPL to configure size and base
address of DRAM. Let's preserve it in SPL devicetree blob.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/risc
Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
them in SPL devicetree blob with bootph-pre-ram property.
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/dts/th1520.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/dts/th1520
16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile
The BROM of TH1520 always initializes UART0's parent clock and
configures the baudrate to 115200. Describe the clock frequency to make
UART function correctly in SPL without introducing CCF.
Signed-off-by: Yao Zi
---
include/configs/th1520_lpi4a.h | 1 +
1 file changed, 1 insertion(+)
, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig | 8
arch/riscv/cpu/cv1800b/Kconfig | 1 +
arch
a.h for SPL.
- Add missing SPDX and copyright header for the DDR driver.
- Link to v1:
https://lore.kernel.org/all/20250426165704.35523-1-zi...@disroot.org/
Yao Zi (10):
riscv: lib: Split out support for T-Head cache management operations
configs: th1520_lpi4a: Add UART clock frequency
riscv
On Mon, May 12, 2025 at 07:53:01AM -0400, e wrote:
> On 2025-05-12 05:57, Leo Liang wrote:
> > On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
> > > [EXTERNAL MAIL]
> > >
> > > The BROM of TH1520 always initializes its clock and configure the
&
On Thu, May 01, 2025 at 03:54:34PM -0500, Nathaniel Hourt wrote:
> On 2025-04-26 23:34, Yao Zi wrote:
> > On Sat, Apr 26, 2025 at 06:25:50PM -0500, Nathaniel wrote:
> > > On Apr 26 2025, at 1:30 am, Yao Zi wrote:
> > > > On Fri, Apr 25, 2025 at 12:43:08P
On Mon, Apr 28, 2025 at 08:49:43AM -0600, Tom Rini wrote:
> On Mon, Apr 28, 2025 at 03:57:27AM +0000, Yao Zi wrote:
> > On Sun, Apr 27, 2025 at 10:16:27AM -0600, Tom Rini wrote:
> > > On Sun, Apr 27, 2025 at 03:46:56PM +, Yao Zi wrote:
> > > > On Sun, Apr 27, 2025
On Sun, Apr 27, 2025 at 10:16:27AM -0600, Tom Rini wrote:
> On Sun, Apr 27, 2025 at 03:46:56PM +0000, Yao Zi wrote:
> > On Sun, Apr 27, 2025 at 05:19:04PM +0200, Heinrich Schuchardt wrote:
> > > Am 27. April 2025 16:50:10 MESZ schrieb Yao Zi :
> > > >Clang's pre
On Sun, Apr 27, 2025 at 05:19:04PM +0200, Heinrich Schuchardt wrote:
> Am 27. April 2025 16:50:10 MESZ schrieb Yao Zi :
> >Clang's preprocessor may emit extra spaces for lines starting with '#'.
> >Lines with these extra characters cannot be handled by Kconfig and wi
aking RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.
Reported-by: Nathaniel Hourt
Signed-off-by: Yao Zi
---
arch/riscv/cpu/cpu.c | 6 ++
arch/riscv/include/asm/global_data.h
Nathaniel Hourt
Signed-off-by: Yao Zi
---
scripts/kconfig/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 079add4d5da..ba30652f01a 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -94,6 +94,7 @@ end
used for now. To test the changes on JH7110 platforms, this
patch[2] must be applied for SPL to function.
[1]:
https://lore.kernel.org/u-boot/932979cb47c4fded7ac19216ca172...@nathaniel.land/
[2]:
https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schucha...@canonical.com/
Yao
On Sat, Apr 26, 2025 at 06:25:50PM -0500, Nathaniel wrote:
> On Apr 26 2025, at 1:30 am, Yao Zi wrote:
> > On Fri, Apr 25, 2025 at 12:43:08PM -0500, Nathaniel Hourt wrote:
> > > Hi, all
> > >
> > > I am trying to build u-boot and SPL for my Mars board (riscv,
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
them in SPL devicetree blob with bootph-pre-ram property.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
Memory node is necessary for TH1520 SPL to configure size and base
address of DRAM. Let's preserve it in SPL devicetree blob.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dt
Drop filename property for proper U-Boot entry since binman takes
"u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries.
This follows efe9c12322b ("riscv: dts: binman.dtsi: Switch to
u-boot-nodtb entry for proper U-Boot") to clean binman.dtsi up.
Signed-off-by:
On Sat, Apr 26, 2025 at 04:56:58PM +, Yao Zi wrote:
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
>
> Currently the driver is only capable of i
Add binman configuration for TH1520 SoC, whose BROM loads the image
combined into SRAM and directly jumps to it. The configuration creates
u-boot-with-spl.bin where the SPL code locates at the start and the DDR
firmware is shipped.
Signed-off-by: Yao Zi
---
arch/riscv/dts/thead-th1520
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index ef84d8cc265..b908eb37e41
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A
port. Update the documentation of support status and build
instructions.
Signed-off-by: Yao Zi
---
doc/board/thead/lpi4a.rst | 58 +--
1 file changed, 55 insertions(+), 3 deletions(-)
diff
Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520-l
16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi
---
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile | 4 +
drivers/ram
16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi
---
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile | 4 +
drivers/ram
, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi
---
arch/riscv/Kconfig | 8
arch/riscv/cpu/cv1800b/Kconfig | 1 +
arch/riscv/cpu/cv1800b/Makefile
Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi
---
arch/riscv/Kconfig
The BROM of TH1520 always initializes its clock and configure the
baudrate to 115200. Add a clock-frequency property to provide such
information without introducing CCF to SPL.
Signed-off-by: Yao Zi
---
arch/riscv/dts/th1520.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv
.
[1]: https://lore.kernel.org/all/20250416162533.1396-1-zi...@disroot.org/
Yao Zi (10):
riscv: lib: Split out support for T-Head cache management operations
riscv: dts: th1520: Add clock-frequency for UART0
riscv: cpu: Add TH1520 CPU support
ram: thead: Add initial DDR controller support for TH
e board. If I pass a working SPL
Have you tried to apply this patch[1]? U-Boot support for JH7110 is
broken at least in v2025.04 release afaik.
Best regards,
Yao Zi
[1]:
https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schucha...@canonical.com/
> I downloaded, it logs some output
five: use consistent formatting
> doc: starfive: use jh7110_common.rst
> doc: jh7110: describe debug UART
>
> Huan Zhou (2):
> riscv: dts: k1: add pinctrl property in dts.
> config: Enable pinctrl in bananapi-f3
>
> Minda Chen (1):
> MAINT
t;)
> Suggested-by: Marek Vasut
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 4
> 1 file changed, 4 insertions(+)
Tested-by: Yao Zi
Sadly this didn't catch up with v2025.04, in which JH7110 SoCs are
broken...
> diff --git a/
44
> --- a/tools/fit_common.c
> +++ b/tools/fit_common.c
> @@ -123,6 +123,7 @@ err:
> close(fd);
> if (delete_on_error)
> unlink(fname);
> + free(ptr);
>
> return -1;
> }
> --
> 2.34.1
Thanks,
Yao Zi
On Thu, Apr 17, 2025 at 03:35:50PM -0600, Simon Glass wrote:
> Hi Yao,
>
> On Wed, 16 Apr 2025 at 10:25, Yao Zi wrote:
> >
> > Switch to u-boot-nodtb entry which precisely represents a proper U-Boot
> > and could be matched with u_boot_any. This allows RISC-V ports tha
rt in linkerscript of both SPL and
proper U-Boot to ensure binman_sym functions correctly with the default
binman.dtsi. The paired symbol, __image_copy_end, is introduced as well
for completeness.
Signed-off-by: Yao Zi
Reviewed-by: Simon Glass
---
arch/riscv/cpu/u-boot-spl.lds | 2 ++
arch/riscv/
7;/binman/spl-img/mkimage/u-boot-spl/u-boot-spl-nodtb':
Entry 'u-boot-any' not found in list (u-boot-spl-nodtb,
u-boot-spl-dtb,u-boot-spl,mkimage,spl-img)
Fixes: 90602e779d3 ("riscv: dts: starfive: generate u-boot-spl.bin.normal.out")
Suggested-by: Jonas K
ifive: unleashed: Switch to use binman to generate
u-boot.itb")
Suggested-by: Jonas Karlman
Signed-off-by: Yao Zi
---
arch/riscv/dts/binman.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405faca574..b7656423
d patch to prevent binman from relocating SPL of VisionFive 2
- Fix typo (one missing underscore) in linkerscript and collect Simon's
r-b tag.
- Link to v1:
https://lore.kernel.org/u-boot/20250407033744.4025-1-zi...@disroot.org/
Yao Zi (3):
riscv: dts: binman.dtsi: Switch to u-boot-nodtb
On Mon, Apr 07, 2025 at 01:10:32PM +0200, Jonas Karlman wrote:
> Hi,
>
> On 2025-04-07 05:37, Yao Zi wrote:
> > Binman looks for __image_copy_start to determine the base address of an
> > entry if elf-base-sym isn't specified, which is missing in RISC-V port.
> >
On Mon, Apr 07, 2025 at 01:22:37PM +0200, Jonas Karlman wrote:
> Hi,
>
> On 2025-04-07 05:37, Yao Zi wrote:
> > The default binman configuration of RISC-V wraps proper U-Boot into a
> > FIT image instead of shipping a plain image, thus there's no
> > "u_boot
On Mon, Apr 07, 2025 at 10:50:07PM +1200, Simon Glass wrote:
> Hi Yao,
>
> On Mon, 7 Apr 2025 at 15:38, Yao Zi wrote:
> >
> > The default binman configuration of RISC-V wraps proper U-Boot into a
> > FIT image instead of shipping a plain image, thus there's no
&
- qemu-riscv64_defconfig
- sifive_unleashed_defconfig
- starfive_visionfive2_defconfig
with either real hardware or QEMU.
Thanks for your time and review.
Yao Zi (2):
spl: riscv: Disable SPL_BINMAN_UBOOT_SYMBOLS by default
riscv: Provide __image_copy_{start_end} symbols in linkerscript
arch/riscv/cpu/u-boot-s
rt in linkerscript of both SPL and
proper U-Boot to ensure binman_sym functions correctly with the default
binman.dtsi. The paired symbol, __image_copy_end, is introduced as well
for completeness.
Signed-off-by: Yao Zi
---
arch/riscv/cpu/u-boot-spl.lds | 2 ++
arch/riscv/cpu/u-boot.lds | 3 +++
2
sage like
Section '/binman/spl-img': Symbol '_binman_u_boot_any_prop_size'
in entry '/binman/spl-img/mkimage/u-boot-spl/u-boot-spl-nodtb':
Entry 'u-boot-any' not found in list (u-boot-spl-nodtb,
u-boot-spl-dtb,u-boot-spl,mkimage,spl-im
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