d upstream DT changes (already landed through recent
> subtree merge of DT changes in Linux 6.16)
> - Link to v1:
> https://lore.kernel.org/r/20250624-db410c-autoboot-fixes-v1-0-d96c97ae4...@linaro.org
Nice fixes and cleanup, FWIW:
Acked-by: Sumit Garg
-Sumit
>
> ---
>
work for
> Tom, if I understand correctly?
>
> Instead add or modify this dts as
> arch/riscv/dts/jh7110s-starfive-visionfive-2-lite-u-boot.dtsi filename.
That's right. dts/upstream subtree isn't allowed to be directly patched
but it is rather synced regularly with devicetree-rebasing. So please
follow documentation documentation here [1].
[1]
https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing
-Sumit
On Wed, Aug 13, 2025 at 03:50:21PM +0200, Casey Connolly wrote:
> Hi Sumit,
>
> On 24/07/2025 13:19, Sumit Garg wrote:
> > From: Sumit Garg
> >
> > Currently fastboot mode is enumerated as VID/PID: : which is
> > not appropriate. On Qcom platforms, f
ue was found by Smatch.
>
> Signed-off-by: Andrew Goodbody
> ---
> drivers/phy/qcom/phy-qcom-snps-eusb2.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Sumit Garg
-Sumit
>
> diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c
> b/drivers
From: Sumit Garg
Currently fastboot mode is enumerated as VID/PID: : which is
not appropriate. On Qcom platforms, fastboot mode is rather enumerated
as VID/PID: 18d1:d00d in ABL or from fastboot.efi app. So lets use the
same VID/PID pair in U-Boot to represent fastboot mode.
Signed-off
From: Sumit Garg
Currently fastboot mode is enumerated as VID/PID: : which is
not appropriate. On Qcom platforms, fastboot mode is rather enumerated
as VID/PID: 18d1:d00d in ABL or from fastboot.efi app. So lets use the
same VID/PID pair in U-Boot to represent fastboot mode.
Signed-off
by
> - Rebased on next
> - Link to v1:
> https://lore.kernel.org/r/20250401-topic-sm8x50-pmic-gpio-pinctrl-new-v1-0-74077ef0b...@linaro.org
>
The alignment with Linux driver is really a good step, feel free to add:
Acked-by: Sumit Garg
-Sumit
> ---
> Neil Armstrong (2):
> gpio:
rry-picks seems fine to me. Feel free to add following to
those DT cherry-picks:
Reviewed-by: Sumit Garg
-Sumit
>
> k3-ddrss is using absolute register accesses at the moment. I am trying
> to submit syscon DT patches upstream to access these through syscon,
> unfortunately ther
don't think
this patch as it is applied upstream since the manual patch isn't
allowed for dts/upstream subtree. You can rather have a *-u-boot.dtsi
for this change.
-Sumit
>
> diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
> b/dts/upstream/src/arm64/q
scale => arch/arm/dts}/imx91.dtsi | 17 -
It is really unfortunate that this DT landed in dts/upstream without
anything in upstream kernel. Direct patching of dts/upstream is not
allowed but you should only be able to do cherry picking as described
here [1].
FWIW:
Reviewed-
_clk_data
Nice catch!
Reviewed-by: Sumit Garg
-Sumit
>
> drivers/clk/qcom/clock-sc7280.c | 4 ++--
> drivers/clk/qcom/clock-sm8250.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
> ---
> base-commit: d7c449c3d83a986d61e38d1762433c0607caf5c5
> change-id: 202
ad6e762a ]
>
> (cherry picked from commit 76d0d8e00c9ac845ca8d6cbe191cf015ca3a8c16)
> ---
> dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi | 22
> +++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
Reviewed-by: Sumit Garg
-Sumit
>
> diff --git a/dts/upstream
f-by: Heiko Stuebner
>
> [ upstream commit: ede4837a504ca7e5811217060aa8300b8d0cf7f2 ]
>
> (cherry picked from commit cb54a264ecdb9e95b1529e4542e157cb9acded30)
> ---
> dts/upstream/src/arm64/rockchip/px30.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
Nicely done!
Reviewed-
On Tue, Jun 10, 2025 at 10:04:54AM -0600, Tom Rini wrote:
> On Tue, Jun 10, 2025 at 02:22:49PM +0530, Sumit Garg wrote:
> > On Mon, Jun 09, 2025 at 10:22:39AM -0600, Tom Rini wrote:
> > > On Mon, Jun 09, 2025 at 05:07:40PM +0100, Sumit Garg wrote:
> > > > On Mon, Ju
> delete mode 100644 arch/arm/dts/r8a7792-u-boot.dtsi
> delete mode 100644 arch/arm/dts/r8a7793-u-boot.dtsi
> delete mode 100644 arch/arm/dts/r8a7794-u-boot.dtsi
> delete mode 100644 arch/arm/dts/r8a779x-rcar64-u-boot.dtsi
> delete mode 100644 arch/arm/dts/r8a779x-u-boot.dtsi
Gla
On Mon, Jun 09, 2025 at 10:22:39AM -0600, Tom Rini wrote:
> On Mon, Jun 09, 2025 at 05:07:40PM +0100, Sumit Garg wrote:
> > On Mon, Jun 09, 2025 at 09:50:19AM -0600, Tom Rini wrote:
> > > On Mon, Jun 09, 2025 at 04:40:43PM +0100, Sumit Garg wrote:
> > > > On Mon, Ju
On Mon, Jun 09, 2025 at 09:50:19AM -0600, Tom Rini wrote:
> On Mon, Jun 09, 2025 at 04:40:43PM +0100, Sumit Garg wrote:
> > On Mon, Jun 09, 2025 at 03:46:27PM +0200, Dario Binacchi wrote:
> > > Hi Sumit,
> > >
> > > On Mon, Jun 9, 2025 at 3:25 PM Sumit Gar
On Mon, Jun 09, 2025 at 03:46:27PM +0200, Dario Binacchi wrote:
> Hi Sumit,
>
> On Mon, Jun 9, 2025 at 3:25 PM Sumit Garg wrote:
> >
> > Hi Patrice,
> >
> > On Mon, Jun 09, 2025 at 03:15:14PM +0200, Patrice CHOTARD wrote:
> > >
> > >
>
atches in this series aren't clean cherry pick from
upstream. This has to be fixed as otherwise random patches are going to
cause DT sync issues.
-Sumit
>
> Thanks
> Patrice
>
> >
> > arch/arm/dts/stm32h747i-disco-u-boot.dtsi | 104 ++
> >
Ditto for all the subsequent patches in this series.
-Sumit
> ---
>
> dts/upstream/src/arm/st/stm32h7-pinctrl.dtsi | 8
> dts/upstream/src/arm/st/stm32h743i-disco.dts | 2 +-
> dts/upstream/src/arm/st/stm32h743i-eval.dts | 2 +-
> dts/upstream/src/arm/st/stm32h750
include. But let's not worry too much about that at
this point until we see a collision as it's atleast provides a way to
drop redundant DT bindings headers. Thanks for working on this.
FWIW:
Reviewed-by: Sumit Garg
-Sumit
>
> Signed-off-by: Tom Rini
> ---
> This becomes a
| 2 +-
> 6 files changed, 3 insertions(+), 248 deletions(-)
> delete mode 100644 arch/arm/dts/imx93-phyboard-segin.dts
> delete mode 100644 arch/arm/dts/imx93-phycore-som.dtsi
Nice diffstat, FWIW:
Reviewed-by: Sumit Garg
-Sumit
>
> diff --git a/arch/arm/dts/Makef
From: Sumit Garg
The default DIP switch configuration on RB1/2 is to enable flashing
support via USB type-c port either using QDL or fastboot. It's just
cumbersome to get the host mode working in U-Boot via DIP switch toggle
when you need the flashing capability using the type-c port
On Tue, May 13, 2025 at 04:54:22PM +0100, Casey Connolly wrote:
> Hi Sumit,
>
> On 5/12/25 08:01, Sumit Garg wrote:
> > On Fri, May 09, 2025 at 04:54:43PM +0200, Stephan Gerhold wrote:
> > > On Fri, May 09, 2025 at 12:45:20PM +0200, Casey Connolly wrote:
> > > &g
and read it.
>
> Signed-off-by: Aswin Murugan
> ---
> drivers/gpio/msm_gpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Sumit Garg
-Sumit
>
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> index 6783fc756f4..7de332c66ae 10
https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing
-Sumit
> @@ -4,6 +4,25 @@
> #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
> #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
>
> +/* QCS8300 Power Domain Indexes */
> +#define QCS8300_CX 0
On Fri, May 09, 2025 at 04:54:43PM +0200, Stephan Gerhold wrote:
> On Fri, May 09, 2025 at 12:45:20PM +0200, Casey Connolly wrote:
> > On 5/8/25 12:32, Sumit Garg wrote:
> > > From: Sumit Garg
> > >
> > > When debug serial port isn't connected, it is at
From: Sumit Garg
When debug serial port isn't connected, it is at least reported on RB1
that autoboot gets interrupted. It is probably due to random characters
on the UART RX line when disconnected. Lets try to fix this inconsistent
behaviour via enabling AUTOBOOT_KEYED such that the aut
Hi Ilias,
Thanks for your response.
On Tue, May 06, 2025 at 04:26:03PM +0300, Ilias Apalodimas wrote:
> Hi Sumit
>
> On Tue, 6 May 2025 at 15:37, Sumit Garg wrote:
> >
> > + Heinrich
> >
> > On Tue, May 06, 2025 at 01:33:33PM +0200, Casey Connolly wrote:
+ Heinrich
On Tue, May 06, 2025 at 01:33:33PM +0200, Casey Connolly wrote:
>
>
> On 5/6/25 09:13, Sumit Garg wrote:
> > Hi Casey,
> >
> > On Fri, Apr 11, 2025 at 05:03:33PM +0200, Caleb Connolly wrote:
> > > The initial capsule update support only worked o
ate
process in U-Boot:
=> efidebug capsule disk-update
=>
Is there a known issue? After enabling debug logs, I see the capsule
update invocation bails out from here [1].
[1]
https://source.denx.de/u-boot/u-boot/-/blob/master/lib/efi_loader/efi_capsule.c?ref_type=heads#L1037
-Sumit
>
From: Sumit Garg
RB1 and RB2 have three root compatibles where the last one can't be used
to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first
compatible to retrieve the SoC name.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/board.c
On Mon, May 05, 2025 at 09:26:09AM +0200, neil.armstr...@linaro.org wrote:
> On 05/05/2025 09:23, Neil Armstrong via groups.io wrote:
> > Hi,
> >
> > On 23/04/2025 07:11, Sumit Garg wrote:
> > > From: Sumit Garg
> > >
> > > RB1 and RB2 have th
On Wed, Apr 23, 2025 at 10:41:32AM +0530, Sumit Garg wrote:
> From: Sumit Garg
>
> RB1 and RB2 have three root compatibles where the last one can't be used
> to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first
> compatible to retrieve the SoC name.
>
On Fri, May 02, 2025 at 04:32:44PM +0200, Casey Connolly wrote:
>
>
> On 5/2/25 14:37, Sumit Garg wrote:
> > On Fri, May 02, 2025 at 02:16:53PM +0200, Casey Connolly wrote:
> > > Hi Sumit,
> > >
> > > On 5/2/25 12:50, Sumit Garg wrote:
> > >
On Fri, May 02, 2025 at 02:16:53PM +0200, Casey Connolly wrote:
> Hi Sumit,
>
> On 5/2/25 12:50, Sumit Garg wrote:
> > Hi Casey
> >
> > On Fri, Apr 11, 2025 at 05:03:33PM +0200, Caleb Connolly wrote:
> > > The initial capsule update support only worked on t
ature. I think
currently we are missing any documentation from this patch-set. IOW, how
one can test updating U-Boot via EFI firmware capsules? I suppose we are
using here dynamic GUID generation while creating update capsules,
right?
-Sumit
>
> ---
> Changes in v2:
> - Restric
Hi Casey,
On Fri, Apr 11, 2025 at 02:47:45PM +0200, Caleb Connolly wrote:
> There are 134 pins not 133, oops! This fixes the sdcard on the RB1 as
> the pins now all get configured correctly.
>
> Fixes: 0ecb8cfcb930 ("pinctrl: qcom: add qcm2290 pinctrl driver")
>
On Thu, Apr 10, 2025 at 05:32:08PM +0530, Varadarajan Narayanan wrote:
> Move to SYSRESET for implementing the reset command.
>
> Signed-off-by: Varadarajan Narayanan
> ---
> configs/qcs9100_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Sumit Garg
-Sumit
;,
> + .id = UCLASS_SYSRESET,
> + .ops = &qcom_psci_sysreset_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/sysreset.h b/include/sysreset.h
> index ff20abdeed3..8bda9703cd9 100644
> --- a/include/sysreset.h
> +++ b/include/sysreset.h
> @@ -21,6 +21,8 @@ enum sysreset_t {
> SYSRESET_POWER,
> /** @SYSRESET_POWER_OFF: turn off power */
> SYSRESET_POWER_OFF,
> + /** @SYSRESET_EDL: reset and boot into Emergency DownLoader */
Is it Qcom specific then add proper comments here?
-Sumit
> + SYSRESET_EDL,
> /** @SYSRESET_COUNT: number of available reset types */
> SYSRESET_COUNT,
> };
> --
> 2.34.1
>
symbol error while compiling. So, do not include it if CONFIG_SYSRESET
> is enabled.
I would rather like to see all Qcom platforms migrating to SYSRESET but
this looks reasonable to me as of now, FWIW:
Reviewed-by: Sumit Garg
-Sumit
>
> Signed-off-by: Varadarajan Narayanan
&
t;
> Signed-off-by: Stephan Gerhold
> ---
> Stephan Gerhold (3):
> board: dragonboard410c: Fix button cmd name
> board: dragonboard410c: Drop custom reduced malloc size
> board: dragonboard410c: Enable support for KASLR in Linux
>
Nicely done, FWIW:
Reviewed-
-apq8016-clock-fixes2-v1-0-bfc9dd933...@linaro.org
>
Nice fixups, FWIW:
Reviewed-by: Sumit Garg
-Sumit
> ---
> Stephan Gerhold (6):
> clk: qcom: apq8016: Fix SDCC clock addresses
> clk: qcom: Move qcom_gate_clk_en() to C file
> clk: qcom: Use setbits_le32() for qcom_ga
board to OF_UPSTREAM
> ARM: dts: stm32: convert stm32mp15 board to OF_UPSTREAM
> configs: stm32: introduce stm32mp15-odyssey_defconfig
> clk: stm32mp1: fix DSI clock setting
> ARM: dts: stm32: convert stm32mp2 board to OF_UPSTREAM
Glad to see the diff with OF_UPSTREAM ad
ig| 7 +++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/qcom-wdt.c | 117
>
> 4 files changed, 127 insertions(+)
>
Looks reasonable to me, FWIW:
Acked-by: Sumit Garg
-Sumit
> diff --git a/configs/qcom_defconfig
From: Sumit Garg
RB1 and RB2 have three root compatibles where the last one can't be used
to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first
compatible to retrieve the SoC name.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/board.c | 12 ++--
1
de in U-Boot like it's bigger
> sibling the RB2.
FWIW, for the series:
Tested-by: Sumit Garg
-Sumit
>
> ---
> Caleb Connolly (6):
> event: signal when livetree has been built
> mach-snapdragon: use EVT_OF_LIVE_INIT to apply DT fixups
> mach-snapdr
On Tue, Apr 08, 2025 at 04:43:49PM +0200, Caleb Connolly wrote:
>
>
> On 4/8/25 15:46, Sumit Garg wrote:
> > On Tue, Apr 08, 2025 at 02:17:29PM +0200, Caleb Connolly wrote:
> > >
> > >
> > > On 4/7/25 15:28, Sumit Garg wrote:
> > > > From
, "qcom,qrb2210-rb1")) {
> - fdt_for_each_node_by_compatible(node, blob, 0, "snps,dwc3") {
> - log_debug("%s: Setting 'dr_mode' to OTG\n",
> fdt_get_name(blob, node, NULL));
> - fdt_setprop_string(fdt, node, "dr_mode", "otg");
> - break;
> - }
> - }
> -
> return 0;
> }
We should now be able to drop OF_BOARD_SETUP from qcom_defconfig and
this API.
With that:
Reviewed-by: Sumit Garg
-Sumit
| 67
> ++++
> 3 files changed, 91 insertions(+)
Reviewed-by: Sumit Garg
-Sumit
>
> diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h
> b/arch/arm/mach-snapdragon/include/mach/gpio.h
> index
> cc8f405e20b4392cf9226b805bc8
From: Sumit Garg
Recent addition of support for SDM660 inadvertently broke USB PHY power
on sequence on RB1/RB2 and others with following error:
starting USB...
Bus usb@4e0: QUSB2PHY pll lock failed: status reg = 0
qcom-qusb2-phy phy@1613000: PHY: Failed to power on phy@1613000: -16.
Can&#
ed-off-by: Caleb Connolly
> ---
> drivers/pinctrl/qcom/pinctrl-qcm2290.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Nice catch!
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
> b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
> ind
On Wed, Apr 09, 2025 at 07:17:27PM +0200, Caleb Connolly wrote:
> The device name is always clk_qcom... Not very useful.
>
> Signed-off-by: Caleb Connolly
> ---
> drivers/clk/qcom/clock-qcm2290.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: S
2 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/of_fixup.c
> b/arch/arm/mach-snapdragon/of_fixup.c
> index
> d4e24059212c552de7fa7555d2ab8a1ea4fc4cb2..b39036e8e0890fdf834a0dfe6966ef3dd365f3d2
> 100644
> --- a/arch/arm/mach-sn
t; ---
> arch/arm/mach-snapdragon/board.c | 1 -
> arch/arm/mach-snapdragon/of_fixup.c | 7 ++-
> arch/arm/mach-snapdragon/qcom-priv.h | 14 --
> 3 files changed, 6 insertions(+), 16 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/a
are bound.
>
> Signed-off-by: Caleb Connolly
> ---
> common/event.c | 3 +++
> include/event.h | 9 +
> lib/of_live.c | 3 +++
> 3 files changed, 15 insertions(+)
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/common/event.c b/common/event
On Wed, Apr 09, 2025 at 07:23:09PM +0200, Caleb Connolly wrote:
>
>
> On 4/9/25 14:35, Sumit Garg wrote:
> > On Tue, Apr 08, 2025 at 04:43:49PM +0200, Caleb Connolly wrote:
> > >
> > >
> > > On 4/8/25 15:46, Sumit Garg wrote:
> > > > On
From: Sumit Garg
Currently the msm_sdhci doesn't yet support DLL configurations which are
required to enable bus speeds greater that 100MHz. So disable HS200 mode
support as of now as it requires bus speeds of 200MHz.
This should fix eMMC issues reported on RB1/RB2 although it should fix
i
-76dfea80b...@linaro.org/
Sumit Garg (2):
qcom_defconfig: Disable MMC HS200 mode support
phy: phy-qcom-qusb2: Fix USB PHY power on sequence
configs/qcom_defconfig| 1 -
drivers/phy/qcom/phy-qcom-qusb2.c | 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
--
2.43.0
On Tue, Apr 08, 2025 at 02:13:55PM +0200, Caleb Connolly wrote:
>
>
> On 4/8/25 06:29, Sumit Garg wrote:
> > On Mon, Apr 07, 2025 at 04:30:44PM +0200, Caleb Connolly wrote:
> > >
> > >
> > > On 4/7/25 15:28, Sumit Garg wrote:
> > > > From
On Tue, Apr 08, 2025 at 02:17:29PM +0200, Caleb Connolly wrote:
>
>
> On 4/7/25 15:28, Sumit Garg wrote:
> > From: Sumit Garg
> >
> > Add U-Boot override for RB1 to for USB in host mode as OTG mode isn't
> > supported. Also, disable sdhc_2 as it's cur
On Mon, Apr 07, 2025 at 04:30:44PM +0200, Caleb Connolly wrote:
>
>
> On 4/7/25 15:28, Sumit Garg wrote:
> > From: Sumit Garg
> >
> > Currently the msm_sdhci doesn't yet support DLL configurations which are
> > required to enable bus speeds grea
Add U-Boot override for RB1 to for USB in host mode as OTG mode isn't
supported. Also, disable sdhc_2 as it's currently not supported, sdhc_1
works fine though.
Signed-off-by: Sumit Garg
---
arch/arm/dts/qrb2210-rb1-u-boot.dtsi | 11 +++
1 file changed, 11 insertions(+)
c
x27;t supported. Along with that disable sdhci_2 which doesn't work
as of now.
There is another patch related to clk_stub posted here [1] which allows
the MMC clocks to be probed properly.
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20250407120536.236003-4-jorge.rami...@oss.qualcomm.c
Currently the msm_sdhci doesn't yet support DLL configurations which are
required to enable bus speeds greater that 100MHz. So disable HS200 mode
support as of now as it requires bus speeds of 200MHz.
This should fix eMMC issues reported on RB1.
Signed-off-by: Sumit Garg
---
co
From: Sumit Garg
Add U-Boot override for RB1 to for USB in host mode as OTG mode isn't
supported. Also, disable sdhc_2 as it's currently not supported, sdhc_1
works fine though.
Signed-off-by: Sumit Garg
---
arch/arm/dts/qrb2210-rb1-u-boot.dtsi | 11 +++
1 file changed, 11
From: Sumit Garg
Currently the msm_sdhci doesn't yet support DLL configurations which are
required to enable bus speeds greater that 100MHz. So disable HS200 mode
support as of now as it requires bus speeds of 200MHz.
This should fix eMMC issues reported on RB1.
Signed-off-by: Sumit
From: Sumit Garg
The eMMC on RB1 boards supports HS200 mode but currently the msm_shdci
driver in U-Boot is missing DLL configuration required for HS200 mode to
work. Hence disable HS200 for now until proper support is in place.
Apart from that, add DT override for USB to work in host mode as
roc" },
> { .compatible = "qcom,glink-rpm" },
> { .compatible = "qcom,rpm-sm6115" },
This platform specific compatible can be dropped now.
Apart from that, feel free to add:
Reviewed-by: Sumit Garg
-Sumit
> + { .compatible = "qcom,glink-smd-rpm" },
> { }
> };
>
> --
> 2.34.1
>
s: 7235dbedfce3 (mach-snapdragon: enable DM_USB_GADGET by default)
> Signed-off-by: Caleb Connolly
> ---
> configs/hmibsc_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig
&g
es what
> > > you're expecting too.
> >
> > When you merge subtree, the patch is not modified and it lives in
> > separate repo. No one sends them over lists, no one modifies them.
> > Unlike here (even if modification did not happen, person was touching it
> > so how can anyone be sure? That's not a scripted process).
>
> We merge the subtree on tags, and people cherry-pick commits in between
> tags when needed. This is a case of the latter, which is why it says "[
> upstream commit ]" in the commit message, which is the usual case.
Although we have tooling to pick patches from devicetree-rebasing tree
but I can see Krzysztof's concerns here. We can't be sure if developer
has touched the cherry picked patch or not but I suppose there would be
similar concerns for the stable backports for Linux too. So IMHO, it's
really upto maintainer applying those cherry-picked patches to see if
there is any difference from upstream.
However, there is an additional process change what we can do here is
for the developer to list just the commit IDs for the patches to be
cherry picked in dts/upstream in the cover letter. This way the
maintainer can just directly use the tooling to cherry pick those
patches before applying the patch-set.
Tooling already available for cherry-picking subtree commits as:
$ ./tools/update-subtree.sh pick dts
-Sumit
hes upstream to access these through syscon,
> unfortunately there is ongoing discussion regarding syscon.
>
> I tested this on am62a.
>
> Best,
> Markus
>
> To: Tom Rini
> To: Vignesh Raghavendra
> To: Bryan Brattlof
> To: Sumit Garg
> Cc: u-boot@lists.denx.de
On Thu, Mar 06, 2025 at 10:39:28AM +, manikanda...@microchip.com wrote:
> Hi Sumit,
>
> On 06/03/25 12:30 pm, Sumit Garg wrote:
> > [Some people who received this message don't often get email from
> > sumit.g...@kernel.org. Learn why this is import
o drop local include/dt-bindings/clock/at91.h from
U-Boot tree. Won't that just work fine?
-Sumit
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 10f7f1fd180..d50841a4a41 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -464,7 +464,7 @@ F:drivers/memory/atmel-ebi.c
>
On Mon, Mar 03, 2025 at 10:26:15AM +, manikanda...@microchip.com wrote:
> Hi Eugen and Sumit,
>
> On 28/02/25 5:07 pm, Sumit Garg wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On Fri, 28
On Fri, 28 Feb 2025 at 16:45, Eugen Hristev wrote:
>
>
>
> On 2/28/25 12:58, Sumit Garg wrote:
> > On Fri, 28 Feb 2025 at 15:20, wrote:
> >>
> >> Hi Eugen,
> >>
> >> On 27/02/25 7:48 pm, Eugen Hristev wrote:
> >>> EXTERNAL EMAIL:
ou ported
> from Linux are about to be split out into SoC specific headers.
> Discussion over here:
>
> https://lore.kernel.org/linux-clk/20250210164506.495747-2-...@thorsis.com/
AFAICS, currently you are just creating duplicate SoC headers. I
suppose you don't plan to drop bits
On Fri, 28 Feb 2025 at 15:20, wrote:
>
> Hi Eugen,
>
> On 27/02/25 7:48 pm, Eugen Hristev wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On 2/27/25 12:37, manikanda...@microchip.com wrote:
&g
Update Sumit Garg's email address to @kernel.org.
Signed-off-by: Sumit Garg
---
.mailmap| 1 +
MAINTAINERS | 7 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/.mailmap b/.mailmap
index dc11775d4e7..50dd61dce76 100644
--- a/.mailmap
+++ b/.mailmap
@@ -123,6 +
You should rather drop these local DT bindings headers which will
allow dts/upstream/include/dt-bindings/clock/at91.h to be included
automatically.
-Sumit
>
> Signed-off-by: Manikandan Muralidharan
> ---
> include/dt-bindings/clk/at91.h | 3 +++
> include/dt-bindings/clock/at91.h |
> arch/arm/dts/at91-sam9x75_curiosity.dts | 374 ++
Ditto, try to enable OF_UPSTREAM.
-Sumit
> 3 files changed, 455 insertions(+)
> create mode 100644 arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi
> create mode 100644 arch/arm/dts/at91-sam9x75_curios
cetree/control.html#where-do-i-get-a-devicetree-file-for-my-board
-Sumit
> 1 file changed, 1273 insertions(+)
> create mode 100644 arch/arm/dts/sam9x7.dtsi
>
> diff --git a/arch/arm/dts/sam9x7.dtsi b/arch/arm/dts/sam9x7.dtsi
> new file mode 100644
> index 000..35c81fa
y
>
> v3: Removed unnecessary comment
> ---
> configs/qcom_ipq9574_mmc_defconfig | 83 ++
> 1 file changed, 83 insertions(+)
> create mode 100644 configs/qcom_ipq9574_mmc_defconfig
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/configs/qcom_ipq957
On Tue, 18 Feb 2025 at 14:25, Varadarajan Narayanan
wrote:
>
> Enable the IPQ9574 clock & pinctrl driver in the Qualcomm defconfig.
>
Does this really have to be enabled in the Qualcomm defconfig if it
can't be supported due to size constraints?
-Sumit
> Reviewed-by: Cal
+# CONFIG_PINCTRL_QCOM_SM8650 is not set
> +# CONFIG_PMIC_CHILDREN is not set
> +# CONFIG_PMIC_QCOM is not set
> +# CONFIG_POWER_DOMAIN is not set
> +# CONFIG_PXE_UTILS is not set
> +# CONFIG_QCOM_HYP_SMMU is not set
> +# CONFIG_REGEX is not set
> +# CONFIG_RGMII is not set
> +# CONFIG_SHA1_LEGACY is not set
> +# CONFIG_SHA256_LEGACY is not set
> +# CONFIG_UFS is not set
> +# CONFIG_USB is not set
> +# CONFIG_VIDEO is not set
We should rather create a separate defconfig for this platform. It's
just redundant to include generic defconfig and then make it platform
specific.
-Sumit
> --
> 2.34.1
>
| 7 +++
> 1 file changed, 7 insertions(+)
> create mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
> b/arch/riscv/dts/jh7110-deepcomputing-fml13v0
einrich Schuchardt
> ---
> configs/starfive_visionfive2_defconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/configs/starfive_visionfive2_defconfig
> b/configs/starfive_visionfive2_defconfig
> index c3f2142a
On Wed, 22 Jan 2025 at 16:49, Andre Przywara wrote:
>
> On Wed, 22 Jan 2025 12:03:24 +0530
> Sumit Garg wrote:
>
> Hi Sumit,
>
> > On Sun, 19 Jan 2025 at 22:13, Andre Przywara wrote:
> > >
> > > This series converts boards with the Allwinner F1C100s/F
ependencies from dts/upstream tree. This will at least give folks who
care about these boards a chance to uprev the corresponding DTs.
-Sumit
>
> I compiled all boards with and without this series applied: the
> resulting u-boot.dtb files were always identical.
>
> Please have
o see DT subtree resync, it has been smooth up-revs then what I
had expected initially when we introduced it.
-Sumit
> --
> Tom
3: Removed duplicates
> CONFIG_ARM, CONFIG_PHY_QCOM_QMP_UFS & CONFIG_QCOM_UFS
> v2: Use qcs9100-ride-r3 for default DT instead of sa8775p-ride-r3
> ---
> configs/qcs9100_defconfig | 18 ++
> 1 file changed, 18 insertions(+)
> create mode 100644 configs/qcs9100_defconfig
com/qcs9100-ride.dts| 11 +++
> 2 files changed, 22 insertions(+)
> create mode 100644 dts/upstream/src/arm64/qcom/qcs9100-ride-r3.dts
> create mode 100644 dts/upstream/src/arm64/qcom/qcs9100-ride.dts
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/dts/upstream/src/arm64
; +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_BASE=0xA8C000
> +CONFIG_DEBUG_UART_MSM_GENI=y
> +CONFIG_DEBUG_UART_CLOCK=14745600
> +
> +# Address where U-Boot will be loaded
> +CONFIG_TEXT_BASE=0xaf00
> +CONFIG_REMAKE_ELF=y
> +
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs9100-ride-r3"
> +
> +CONFIG_PHY_QCOM_QMP_UFS=y
> +CONFIG_QCOM_UFS=y
Again, these are already defined in qcom_defconfig.
-Sumit
> --
> 2.34.1
>
mm I see, well that's a pickle. I don't think we have a process yet for
> handling these cases where we're blocked on a DTS sync.
>
> I would rather avoid creating this weird situation where we use the
> sa8775p dts and pretend it's a different board especially if it&
On Sat, 4 Jan 2025 at 07:28, FUKAUMI Naoki wrote:
>
> Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
>
> Changes in v5:
> - Rebase on top of latest next branch
> - Drop PATCH 1/5
>
For the series:
Acked-by: Sumit Garg
-Sumit
> Cristian Cioca
* branchmaster -> FETCH_HEAD
fatal: bad object d7bb71e69f58c1b3665a9f926bf8d3855111bf8e
-Sumit
> Reviewed-by: Kever Yang
> ---
> .../src/arm64/rockchip/rk3588-base.dtsi | 41 +++
> 1 file changed, 41 insertions(+)
>
> diff --git a/
On Fri, 3 Jan 2025 at 18:28, FUKAUMI Naoki wrote:
>
> Hi Sumit,
>
> On 1/3/25 21:53, Sumit Garg wrote:
> > Hi FUKAUMI,
> >
> > On Fri, 3 Jan 2025 at 18:02, FUKAUMI Naoki wrote:
> >>
> >> Enable pcie2x1l2 and related combphy/regulator rou
3de4d73b944cbd1bc1662a9a7a
>From
>https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing
* branchmaster -> FETCH_HEAD
fatal: bad object 4294e32111781b3de4d73b944cbd1bc1662a9a7a
-Sumit
> Reviewed-by: Kever Yang
> ---
> .../arm64/roc
ttps://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing
* branchmaster -> FETCH_HEAD
fatal: bad object b728d4c51f0ce9207daf502f3a85073785c46319
-Sumit
> Reviewed-by: Kever Yang
> ---
> .../src/arm64/rockchip/rk3588s-rock-5a.dts| 30
Hi Tom,
Do you plan to perform DT subtree sync for v6.12 which seems to be due
for some time now?
-Sumit
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