Add scsi command and enable supporting the pcie2sata chip
88SE9170 from Marvell.
Signed-off-by: Po Liu
---
merge to one patch only.
include/configs/ls1043ardb.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/configs/ls1043ardb.h b/include/configs
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, May 17, 2016 12:03 AM
> To: Po Liu
> Cc: u-boot@lists.denx.de; Simon Glass; Bin Meng; o...@andrep.de;
> mark.langsd...@gmail.com
> Subject: Re: [PATCH 1/2] scsi: add PCIe to sata c
Add to the command scsi device list.
Signed-off-by: Po Liu
---
cmd/scsi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/cmd/scsi.c b/cmd/scsi.c
index 8991125..c85fefc 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -31,6 +31,11 @@
#define SCSI_VEND_ID 0x10b9
#define SCSI_DEV_ID 0x5288
Add scsi command and enable supporting the pcie2sata chip
88SE9170 from Marvell.
Signed-off-by: Po Liu
---
include/configs/ls1043ardb.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index bc40b06..c8d03f2 100644
CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes
enviroment;
Signed-off-by: Po Liu
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xe000 to 0x
- change the ddr tlb mapping cond
enviroment;
Signed-off-by: Po Liu
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xe000 to 0x
- change the ddr tlb mapping cond
CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes
enviroment;
Signed-off-by: Po Liu
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xe000 to 0x
- change the ddr tlb mapping cond
CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes
enviroment;
Signed-off-by: Po Liu
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xe000 to 0x
- change the ddr tlb mapping conditi
compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
arch/powerpc/cpu
compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ---
drivers/mtd/nand/fsl_ifc_spl.c | 29
;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu
---
changes for v2:
- seperate the public code and c29xpcie board code;
board/freescale/c29xpcie/Makefile | 15
board/freescale/c29xpcie/cpld.c| 2 +
board/freescale/c29xpcie/spl.c
/C292PCIE_NAND/C293PCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++--
board/freescale/c29xpcie/Makefile | 15
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu
---
Changes for V2
The CPLD registers MSB is powerpc's LSB, and LSB is powerpc's MSB.
It is not convinient for understand. Reverse the value when read
write to the CPLD registers.
Signed-off-by: Po Liu
---
This patch after
http://patchwork.ozlabs.org/patch/278079/
[U-Boot,v2] powerpc/c29xpcie: add DDR
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware,
force that kind of board to be DDR ECC off when booting.
Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on
in uboot enviroment.
Signed-off-by: Po Liu
---
Add this patch after the camelcase patch
http
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware,
force that kind of board to be DDR ECC off when booting.
Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on
in uboot enviroment.
Signed-off-by: Po Liu
---
Add this patch after the camelcase patch
http
Currently, there is only one EEPROM on c29xpcie board which isAT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu
---
Changes for V2
Some boards booting up fail since the DDR ECC chip has bad impedance
in current hardware, make the DDR ECC off when booting.
Signed-off-by: Po Liu
---
include/configs/C29XPCIE.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index
DDR parameters clk_adjust were changed. This can make the DDR
run more stable. The new value were gotten by the DDR testing
tool.
Signed-off-by: Po Liu
---
board/freescale/c29xpcie/ddr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/c29xpcie/ddr.c b/board
This patch re-config the NOR flash timing parameters which could make
the ifc timing more flexible for NOR flash.
The new parameters could fix the problem of hanging at "Flash:"
occasionally when booting the board.
Signed-off-by: Po Liu
---
include/configs/C29XPCIE.h | 8 +-
Currently, there is only one EEPROM on c29xpcie board which isAT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu
---
board/freescale
This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.
Signed-off-by: Po Liu
---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++
include/configs/B4860QDS.h | 2 --
include/configs/P1010RDB.h | 2
t DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by: Mingkai Hu
Signed-off-by: Po Liu
---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293,
replace with CONFIG_C29X
Changes for v3:
- Re
32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu
Singed-off-by: Po Liu
---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293,
replace with CONFIG_C29X
- Adjust the TLB config mode
32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu
Singed-off-by: Po Liu
---
Base on the patch [PATCH 1/2 v3] powerpc/85xx: Add C29x SoC support
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293
32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu
Singed-off-by: Po Liu
---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293,
replace with CONFIG_C29X
- Adjust the TLB config mode
t DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by: Mingkai Hu
Signed-off-by: Po Liu
---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293,
replace with CONFIG_C29X
Changes for v3:
- Re
t DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by: Mingkai Hu
Signed-off-by: Po Liu
---
Base on tree git://git.denx.de/u-boot.git, modified integrate C291/C292/C293 to
C29X.
arch/powerpc/cpu/mpc85xx/Makefile | 2 +
32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu
Singed-off-by: Po Liu
---
Base on tree git://git.denx.de/u-boot.git, modified integrate C291/C292/C293
to C29X.
board/freescale/c29xpcie/Makefile | 34 +++
board
Signed-off-by: Po Liu
---
This patch add readme file for the privious patch "powerpc/c29xpcie: add
support for C29XPCIE board"
board/freescale/c29xpcie/README | 100
1 file changed, 100 insertions(+)
create mode 100644 board/freescale/c29xp
32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu
Singed-off-by: Po Liu
---
Base on the git://git.denx.de/u-boot.git
board/freescale/c29xpcie/Makefile | 34 +++
board/freescale/c29xpcie/c29xpcie.c | 131 +
board
t DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by: Mingkai Hu
Signed-off-by: Po Liu
---
Base on the git://git.denx.de/u-boot.git
arch/powerpc/cpu/mpc85xx/Makefile | 2 +
arch/powerpc/cpu/mpc85xx/c29x_serdes.c
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