DDR parameters clk_adjust were changed. This can make the DDR
run more stable. The new value were gotten by the DDR testing
tool.
Signed-off-by: Po Liu <po....@freescale.com>
---
board/freescale/c29xpcie/ddr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index b017cfd..3337d6c 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -62,7 +62,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
unsigned int ctrl_num)
{
int i;
- popts->clk_adjust = 2;
+ popts->clk_adjust = 4;
popts->cpo_override = 0x1f;
popts->write_data_delay = 4;
popts->half_strength_driver_enable = 1;
--
1.8.0
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