output voltage mode for
> SD2_CMD. 0 High output voltage mode
> 1 Low output voltage mode"
>
> The values are currently negated in code - fixed.
>
> Reported-by: David Jander
> Signed-off-by: Stefano Babic
> CC: Marek Vasut
> CC: David Jander
> ---
>
On Tue, 08 May 2012 15:14:47 +0200
Stefano Babic wrote:
> On 08/05/2012 14:06, David Jander wrote:
>
> >> Go ahead in this direction. Then we can test on these boards (mx51evk /
> >> vision2 / efikamx), the only ones having these issue).
> >
> > I agree we
On Tue, 8 May 2012 14:51:52 +0200
Marek Vasut wrote:
> Dear David Jander,
>
> > On Tue, 08 May 2012 10:46:10 +0200
> >
> > Stefano Babic wrote:
> > > On 07/05/2012 09:11, David Jander wrote:
> > > > Dear Stefano,
> > >
> > >
On Tue, 08 May 2012 10:46:10 +0200
Stefano Babic wrote:
> On 07/05/2012 09:11, David Jander wrote:
> >
> > Dear Stefano,
> >
>
> Hi David,
>
> > Yes, but is none of those boards using 3.15 or 3.3V? If they are, those bits
> > must be cleared!
>
Dear Stefano,
On Sun, 06 May 2012 18:15:18 +0200
Stefano Babic wrote:
> On 04/05/2012 12:08, David Jander wrote:
> >
> > Hi all,
> >
>
> Hi David,
>
> > I discovered a bug in u-boot, that got evident after Freescale updated the
> > i.MX51 data
rmanent damage to them and in
order to not degrade their timing performance."
Seems like we may have a problem here!
I would like to know if anyone is aware of this? Does anyone know of a board
that is actually destroyed this way?
Best regards,
--
David Jander
Protonic Holland.
___
rmanent damage to them and in
order to not degrade their timing performance."
Seems like we may have a problem here!
I would like to know if anyone is aware of this? Does anyone know of a board
that is actually destroyed this way?
Best regards,
--
David Jander
Protonic Holland.
___
would still be nice to know how
> to allocate a section of un-cached RAM in the ARM processor, in so far
> as the question has a single answer! That would allow easy portability
> of drivers that do not know about caches, of which there seems to be many.
I agree. Unfortunately, my time is up for now, and I can't go on with trying
to fix this driver. Maybe I'll pick up after my vacation.
As for now I settled for the ugly solution of keeping dcache disabled while
ethernet is being used :-(
IMHO, doing cache maintenance all over the driver is not an easy or nice
solution. Implementing a non-cached memory pool in the MMU and a corresponding
dma_malloc() sounds like much more universally applicable to any driver.
Best regards,
--
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Protonic Holland.
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Hi Aneesh,
On Wed, 20 Jul 2011 15:59:42 +0530
Aneesh V wrote:
> On Wednesday 20 July 2011 02:51 PM, David Jander wrote:
> > On Wed, 20 Jul 2011 10:56:07 +0200
>
> [snip ..]
>
> >>> Any ideas?
> >>
> >> Yes, one: I had issues with the Marvell E
On Wed, 20 Jul 2011 10:56:07 +0200
Albert ARIBAUD wrote:
> Hi David,
>
> Le 20/07/2011 08:29, David Jander a écrit :
> > On Tue, 19 Jul 2011 14:10:48 +0200
> > David Jander wrote:
> >
> >> On Tue, 19 Jul 2011 13:20:26 +0200
> >> Wolfg
On Tue, 19 Jul 2011 14:10:48 +0200
David Jander wrote:
> On Tue, 19 Jul 2011 13:20:26 +0200
> Wolfgang Denk wrote:
>
> > Dear David Jander,
> >
> > In message <20110719131744.403a81e6@archvile> you wrote:
> > >
> > > Now I finally know wh
ls of flat, direct mapped linear memory to
malloc and dma_malloc from?
That would make fixing broken drivers trivial, and have other benefits (like
video memory coherence when caches are on)!
IMHO, changing the necessary malloc()'s for dma_malloc()'s is a lot less work
and easier to oversee than obscure cache-manipulation and alignment tricks all
over the place What do you think?
Best regards,
--
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On Tue, 19 Jul 2011 13:20:26 +0200
Wolfgang Denk wrote:
> Dear David Jander,
>
> In message <20110719131744.403a81e6@archvile> you wrote:
> >
> > Now I finally know what's wrong and am working on a proposed fix to make
> > this one driver cache-aware.
&g
lot of time debugging the fec_mxc.c driver while
the driver itself wasn't really broken (at least not more than before).
Now I finally know what's wrong and am working on a proposed fix to make this
one driver cache-aware.
Best regards,
--
David Jander
Protonic Holland.
___
Dear Aneesh,
Thanks a lot for your replies.
On Tue, 19 Jul 2011 14:13:34 +0530
Aneesh V wrote:
> On Tuesday 19 July 2011 02:07 PM, David Jander wrote:
> > On Tue, 19 Jul 2011 10:21:12 +0200
> > Albert ARIBAUD wrote:
> >
> >> Hi David,
> >>
> &g
On Tue, 19 Jul 2011 10:21:12 +0200
Albert ARIBAUD wrote:
> Hi David,
>
> Le 19/07/2011 09:44, David Jander a écrit :
> >
> > Hi Stefano,
> >
> > On Mon, 18 Jul 2011 18:55:05 +0200
> > Stefano Babic wrote:
> >
> >> On 07/18/2011 05:18 PM
Hi Stefano,
On Mon, 18 Jul 2011 18:55:05 +0200
Stefano Babic wrote:
> On 07/18/2011 05:18 PM, David Jander wrote:
> >
> > Hi all,
>
> Hi David,
>
> > What is going on here? Why did this work with caches enabled before??
>
> I think cache was always disa
On Mon, 18 Jul 2011 21:46:28 +0530
Aneesh V wrote:
> Hi David,
>
> On Monday 18 July 2011 08:48 PM, David Jander wrote:
> >
> > Hi all,
> >
> > I am busy debugging a problem with the i.MX51 FEC ethernet driver, that
> > stopped working after upgr
in receiving afterwards, but at least this
part seems to work. If I remove either of the two added lines, it stops
working again.
What is going on here? Why did this work with caches enabled before??
Best regards,
--
David Jander
Protonic Holland.
___
U-
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.
Signed-off-by: David Jander
---
Changed in this version:
- Move patch changelog below '---' line.
arch/arm/cpu/armv7/mx5/lowlevel_ini
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.
Changed in this version:
- Added #ifdef CONFIG_MX51 around the workaround
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S |6
On Thu, 14 Jul 2011 14:14:52 +0200
Stefano Babic wrote:
> On 07/14/2011 01:56 PM, David Jander wrote:
> > This check was broken. r3 does not contain the silicon revision anymore, so
> > we need to reload it.
> >
> > Signed-off-by: David Jander
> > ---
>
&g
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it.
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
b/arch/arm
On Thu, 14 Jul 2011 12:49:15 +0200
Stefano Babic wrote:
> On 07/14/2011 12:20 PM, David Jander wrote:
>
> >> However, you also remove the setup for TO2. To fix the TO2 issue, we
> >> should read correctly the revision number (from IIM or from a fixed
> >> add
Hi Stefano,
On Thu, 14 Jul 2011 10:30:11 +0200
Stefano Babic wrote:
> On 07/14/2011 09:11 AM, David Jander wrote:
> > This is a port of the official PLL errata workaround from Freescale to
> > mainline u-boot.
> > The PLL's in the i.MX51 processor can go out o
On Thu, 14 Jul 2011 10:30:11 +0200
Stefano Babic wrote:
> On 07/14/2011 09:11 AM, David Jander wrote:
> > This is a port of the official PLL errata workaround from Freescale to
> > mainline u-boot.
> > The PLL's in the i.MX51 processor can go out of lock due to a meta
On Thu, 14 Jul 2011 10:16:51 +0200
Stefano Babic wrote:
> On 07/14/2011 09:13 AM, David Jander wrote:
> > This check is broken. r3 does not contain the silicon revision.
> >
> > Signed-off-by: David Jander
> > ---
>
> Hi David,
>
> > arc
ither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 38 ++
This check is broken. r3 does not contain the silicon revision.
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
Completed command definitions copied from linux driver source.
Implemented support for AX88178 by copying and rewriting bits and pieces
from the linux asix driver.
Signed-off-by: David Jander
---
drivers/usb/eth/asix.c | 236 +---
include/usb_ether.h
Have you checked latest mainline linux for that processor? I don't know what
drivers you need, but there has been a lot of progress, and chances are it
works better than what you have now :-)
Best regards,
--
David Jander
Protonic Holland.
___
U
On Fri, 27 May 2011 12:13:32 +0200
Stefano Babic wrote:
> On 05/26/2011 07:00 PM, David Jander wrote:
> > i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> > although it is unclear whether all boards and/or chip revisions have this
> > problem. Us
On Thu, 26 May 2011 19:00:14 +0200
David Jander wrote:
> i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> although it is unclear whether all boards and/or chip revisions have this
> problem. Using PLL2 for the core and DDR2 seems to fix the problem.
>
i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
although it is unclear whether all boards and/or chip revisions have this
problem. Using PLL2 for the core and DDR2 seems to fix the problem.
No official errata yet.
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx5
Signed-off-by: David Jander
---
drivers/mtd/spi/spansion.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index d6c1a5f..42cebf6 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
On Tuesday 24 August 2010 06:06:26 pm Mike Frysinger wrote:
> On Tuesday, August 24, 2010 02:39:16 David Jander wrote:
> > On Monday 23 August 2010 06:31:26 pm Mike Frysinger wrote:
> > > On Monday, August 23, 2010 09:12:16 David Jander wrote:
> > > > + {
&g
This patch introduces an extra mask-field in spansion_spi_flash_params
to support flash chips with 1-byte extended ID (like the S25FL032P).
Signed-off-by: David Jander
---
drivers/mtd/spi/spansion.c | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a
On Monday 23 August 2010 06:31:26 pm Mike Frysinger wrote:
> On Monday, August 23, 2010 09:12:16 David Jander wrote:
> > + {
> > + .idcode1 = SPSN_ID_S25FL032A,
> > + .idcode2 = SPSN_EXT_ID_S25FL032P,
> > + .idmask2 = 0xff00,
>
>
This patch introduces an extra mask-field in spansion_spi_flash_params
to support flash chips with 1-byte extended ID (like the S25FL032P).
Signed-off-by: David Jander
---
drivers/mtd/spi/spansion.c | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a
the spansion driver. Will post
a patch later.
Right now I have correct detection of the chip, but the environment is not
saved and read back correctly. Still investigating... maybe some chip
configuration prolem in the spansion driver?
Best regards,
--
David Jander
Protonic Holland.
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On Monday 23 August 2010 10:50:53 am David Jander wrote:
> I am just now picking up where I left last week, so give me a few hours and
> I should have something working, I guess.
Ok, I guess I was pessimistic. There is a weird bug in mxc_spi.c: CPOL is
negated!
I just saw that in the mx5
basically) and fix the pmic driver later,
> > since it is probably not trivial, and needs to be done carefully (you
> > know, one can smoke a board by mistake :-)
>
> I know, this makes funny setting voltages via software
I always say: "Electronics work on smoke. If the smoke escapes, it stops
working" :-)
Best regards,
--
David Jander
Protonic Holland.
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a "char"
> buffer, and the first byte in the buffer is the first byte sent to the
> SPI bus. This is not the case with mxc_spi.c
I know. I thought to do it in two steps: Fix mxc_spi.c with a workaround for
the pmic driver (which amounts to '#define spi_xfer spi_xfer_fsl&#x
On Friday 20 August 2010 12:20:25 pm Stefano Babic wrote:
> David Jander wrote:
> > Great. I'll wait.
> > In the meantime I have just done this to get it working:
> >
> > #ifdef CONFIG_MX31
> > void spi_cs_activate(struct spi_slave *slave)
&g
gt; > + u16 id2;/* 0x48 */
> > + u16 resv7[0x03];
> > + u16 version;/* 0x50 */
> > + u16 resv8[0x03];
> > + u16 id3; /* 0x58 */
> > + u16 resv9[0x03];
> > + u16 sw_reset; /* 0x60 */
> > +}
uct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
unsigned int val = !(mxcs->cfg_reg &
(1 << (slave->cs + MXC_CSPICON_SSPOL)));
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
ruct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
}
On i.MX51 SSPOL is set in the config register, and
! I was just writing the exact same code as in this patch :-(
Thanks a lot anyway.
Best regards,
--
David Jander
Protonic Holland.
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On Friday 20 August 2010 10:12:16 am Stefano Babic wrote:
> David Jander wrote:
> > Signed-off-by: David Jander
> > ---
> > arch/arm/include/asm/arch-mx51/mx51_pins.h |1 +
> > 1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arc
ixes/additions in order to
implement the BSP for PRTLVT2 boards (patch 4/4).
> > +void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
> > +{
> > + u32 pad_reg = IOMUXSW_INPUT_CTL+(input*4);
>
> Code styling, you should add spaces:
>
>
duce a second spi_xfer_fsl() function for all
existing, but broken device drivers that assume fsl-byte-ordering (like the
PMIC driver) and fix the original spi_xfer(). Is that acceptable?
> > + "nfsroot=/srv/home/david/Devel/Sandboxes/LEL/XDH/nfsroot\0" \
> > +
Signed-off-by: David Jander
---
board/Protonic/prtlvt2/Makefile | 48
board/Protonic/prtlvt2/config.mk| 25 ++
board/Protonic/prtlvt2/imximage.cfg | 171
board/Protonic/prtlvt2/prtlvt2.c| 513 +++
board/Protonic/prtlvt2/prtlvt2
Signed-off-by: David Jander
---
include/fsl_pmic.h |2 +-
include/mc13892.h | 41 +
2 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
index e3abde6..2f2aa7d 100644
--- a/include/fsl_pmic.h
+++ b
Signed-off-by: David Jander
---
arch/arm/include/asm/arch-mx51/mx51_pins.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h
b/arch/arm/include/asm/arch-mx51/mx51_pins.h
index ca26f41..c443f13 100644
--- a/arch/arm/include/asm
Signed-off-by: David Jander
---
arch/arm/cpu/armv7/mx51/iomux.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c
index 62b2954..fb48f1c 100644
--- a/arch/arm/cpu/armv7/mx51/iomux.c
+++ b/arch/arm/cpu
initial support for PRTLVT2-based boards.
Signed-off-by: David Jander
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