Re: [U-Boot] [PATCH] Fix some bugs in the EFI support

On Tue, Dec 6, 2011 at 11:35 AM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> Whimper whimper.  This is silly, what happened was that two different >> patches collided when committed.  Mine had the correct change to this >

Re: [U-Boot] [PATCH] Fix some bugs in the EFI support

On Fri, Dec 2, 2011 at 1:59 PM, Simon Glass wrote: > Hi Graeme, > > On Fri, Dec 2, 2011 at 1:28 PM, Graeme Russ wrote: >> Hi Anton, >> >> On 30/11/11 10:39, Gabe Black wrote: >>> The ALLOC_CACHE_ALIGN_BUFFER macro allocates a pointer to a buffer, and the >>> address of the pointer and not the buf

Re: [U-Boot] [PATCH] disk: part_efi: fix regression due to incorrect buffer usage

Tested-by: Anton Staaf Mike, do you think you could pull this into staging as per Wolfgang's recent request for help? Thanks, Anton On Sun, Oct 30, 2011 at 8:44 AM, Mike Frysinger wrote: > Acked-by: Mike Frysinger > -mike > > ___

Re: [U-Boot] [PATCH 1/2] part_efi: Fix compile errors

On Mon, Nov 14, 2011 at 7:19 AM, Sanjeev Premi wrote: > Fix errors noticed after enabling CONFIG_EFI_PARTITION > for the OMAP3 EVM board: There is already a patch for this waiting to be committed. Thanks, Anton > part_efi.c: In function 'print_part_efi': > part_efi.c:133:5: warning: passing

[U-Boot] [PATCH v3 3/4] Tegra2: mmc: Add data transfer completion timeout

and we fail out. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index

[U-Boot] [PATCH v3 4/4] Tegra2: mmc: Factor out mmc_wait_inhibit functionality

This is a well encapsulated section of mmc_send_cmd, by moving it to it's own function it increases the readability of mmc_send_cmd. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c |

[U-Boot] [PATCH v3 1/4] Tegra2: mmc: define register field values in tegra2_mmc.h

This moves the magic numbers sprinkled about the MMC driver to a single location in the header file and gives them meaningful names. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- Changes in v3: - Added back the comments about register

[U-Boot] [PATCH v3 0/4] Tegra2: mmc DMA related fixes

values - Remove patches for bounce buffer implementation Changes in v3: - Added back comments about register values - Shortened #defined macro names Anton Staaf (4): Tegra2: mmc: define register field values in tegra2_mmc.h Tegra2: mmc: Support DMA restarts at buffer boundaries Tegra2: mmc

[U-Boot] [PATCH v3 2/4] Tegra2: mmc: Support DMA restarts at buffer boundaries

the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c

Re: [U-Boot] [PATCH v2 1/4] Tegra2: mmc: define register field values in tegra2_mmc.h

On Thu, Nov 10, 2011 at 8:28 AM, Tom Warren wrote: > Anton, > > -Original Message- > From: Anton Staaf [mailto:robot...@chromium.org] > Sent: Wednesday, November 09, 2011 12:46 PM > To: u-boot@lists.denx.de > Cc: Anton Staaf; Andy Fleming; Tom Warren; Stephen W

[U-Boot] [PATCH v2 1/4] Tegra2: mmc: define register field values in tegra2_mmc.h

This moves the magic numbers sprinkled about the MMC driver to a single location in the header file and gives them meaningful names. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c | 126

[U-Boot] [PATCH v2 2/4] Tegra2: mmc: Support DMA restarts at buffer boundaries

the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c

[U-Boot] [PATCH v2 3/4] Tegra2: mmc: Add data transfer completion timeout

and we fail out. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index

[U-Boot] [PATCH v2 4/4] Tegra2: mmc: Factor out mmc_wait_inhibit functionality

This is a well encapsulated section of mmc_send_cmd, by moving it to it's own function it increases the readability of mmc_send_cmd. Signed-off-by: Anton Staaf Cc: Andy Fleming Cc: Tom Warren Cc: Stephen Warren Cc: Albert Aribaud --- drivers/mmc/tegra2_mmc.c |

[U-Boot] [PATCH v2 0/4] Tegra2: mmc DMA related fixes

values - Remove patches for bounce buffer implementation Anton Staaf (4): Tegra2: mmc: define register field values in tegra2_mmc.h Tegra2: mmc: Support DMA restarts at buffer boundaries Tegra2: mmc: Add data transfer completion timeout Tegra2: mmc: Factor out mmc_wait_inhibit functionality

Re: [U-Boot] [PATCH 1/5] mmc: Tegra2: Support DMA restarts at buffer boundaries

On Wed, Nov 2, 2011 at 6:08 PM, Andy Fleming wrote: > On Thu, Oct 13, 2011 at 4:57 PM, Anton Staaf wrote: >> diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c >> index 8b6f829..195f89d 100644 >> --- a/drivers/mmc/tegra2_mmc.c >> +++ b/drivers/mmc/tegra2

Re: [U-Boot] [PATCH] disk: part_efi: fix regression due to incorrect buffer usage

Thanks Stephen, sorry Doug. :) -Anton On Fri, Oct 28, 2011 at 12:43 PM, Doug Anderson wrote: > Acked-by: Doug Anderson > > ...to be fair though, the regression appears to be caused by a mid-air > collision of Anton's change (f75dd584cdfe29dfdcfd424bb237b9238cfb8fe4) with > my change.  His patc

Re: [U-Boot] [PATCH 3/5] mmc: Tegra2: Factor out mmc_wait_inhibit functionality

On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf wrote: > This is a well encapsulated section of mmc_send_cmd, by moving > it to it's own function it increases the readability of mmc_send_cmd. > > Signed-off-by: Anton Staaf > Cc: Tom Warren > Cc: Stephen Warren Addin

Re: [U-Boot] [PATCH 1/5] mmc: Tegra2: Support DMA restarts at buffer boundaries

On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf wrote: > Currently if a DMA buffer straddles a buffer alignment boundary > (512KiB) then the DMA engine will pause and generate a DMA > interrupt.  Since the DMA interrupt is not enabled it will hang > the MMC driver. > > This patc

Re: [U-Boot] [PATCH 2/5] mmc: Tegra2: Add data transfer completion timeout

On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf wrote: > Currently when no expected completion condition occures in the > mmc_send_cmd while loop that is waiting for a data transfer to > complete the MMC driver just hangs. > > This patch adds an arbitrary 2 second timeout.  If nothing

Re: [U-Boot] Patchwork question

On Fri, Oct 28, 2011 at 10:16 AM, Albert ARIBAUD wrote: > Hi Anton, > > Le 28/10/2011 18:52, Anton Staaf a écrit : >> >> I'm new to patchwork, and am wondering. >> >> Who should change the state of patches there? Should I mark patches >> that have b

[U-Boot] Patchwork question

I'm new to patchwork, and am wondering. Who should change the state of patches there? Should I mark patches that have been applied as Accepted? Or should the tree maintainer do that? Also, should I delegate patches to custodians that I believe should be looking at them? Or should custodians del

[U-Boot] [PATCH] sandbox: Add asm/cache.h for sandbox

This file is required by the new DMA buffer alignment macro. Signed-off-by: Anton Staaf Cc: Simon Glass --- arch/sandbox/include/asm/cache.h | 33 + 1 files changed, 33 insertions(+), 0 deletions(-) create mode 100644 arch/sandbox/include/asm/cache.h diff

[U-Boot] Oops, I broke sandbox

Just realized that I broke the sandbox build by requiring an asm/cache.h file in common.h. I'll send a patch to fix it. -Anton ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v3 0/6] Add cache line alignment support

On Wed, Oct 12, 2011 at 4:55 PM, Anton Staaf wrote: > The cache line alignment issue has gone around a couple of times now.  This > patch set implements all of the details that we have discussed about the > implementation of ALLOC_CACHE_ALIGN_BUFFER.  It also includes patches that use &g

Re: [U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

On Mon, Oct 24, 2011 at 12:45 PM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> I have now run MAKEALL for both ARMv7a and PowerPC successfully. >> There were a number of >> build failures for "powerpc", but no n

Re: [U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

On Mon, Oct 17, 2011 at 4:46 PM, Anton Staaf wrote: > ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel.  It is > used to define the minimum alignement requirement for a DMA buffer.  This > series of patches ensures that it will always be defined in the arch specific >

Re: [U-Boot] [PATCH 2/3] nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

On Mon, Oct 24, 2011 at 2:46 AM, Macpaul Lin wrote: > Add ARCH_DMA_MINALIGN definition to asm/cache.h > > Signed-off-by: Macpaul Lin Acked-by: Anton Staaf > --- >  arch/nds32/include/asm/cache.h |   11 +++ >  1 files changed, 11 insertions(+), 0 deletions(-) >

Re: [U-Boot] [STATUS] "Quality" of patches / testing.

On Tue, Oct 18, 2011 at 10:44 AM, Albert ARIBAUD wrote: > Le 18/10/2011 19:16, Anton Staaf a écrit : > >> I would like to start a thread addressing this question.  I don't think >> the people submitting are running MAKEALL because it has a very high >> barrier to en

Re: [U-Boot] [STATUS] "Quality" of patches / testing.

On Mon, Oct 17, 2011 at 11:23 PM, Wolfgang Denk wrote: > Hi all, > > the patches that have been submitted for this release turn out to of > of shockingly bad quality.  About every other batch of patches I apply > will break building not only for a single board r a few boards, but > for large numbe

Re: [U-Boot] [STATUS] "Quality" of patches / testing.

On Tue, Oct 18, 2011 at 7:05 AM, Simon Glass wrote: > Hi, > > On Tue, Oct 18, 2011 at 2:44 AM, Wolfgang Denk wrote: >> Dear Andreas, >> >> In message <4e9d4552.5040...@gmail.com> you wrote: >>> >>> We should first get a state of "all boards build clean" for a sort of >>> toolchains (I think arm i

[U-Boot] [PATCH v2 11/11] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition

cache line size then the maximum line size of the architecture is used to align DMA buffers. Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Wolfgang Denk Cc: Stefano Babic Cc: Ilya Yanok Cc: Laurence Withers --- include/common.h |8 1 files changed, 8

[U-Boot] [PATCH v2 03/11] nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Scott McNutt --- arch/nios2/include/asm/cache.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h index c78f343..2cc16e4

[U-Boot] [PATCH v2 07/11] avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Reinhard Meyer --- arch/avr32/include/asm/cache.h | 40 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 arch/avr32/include/asm/cache.h diff --git a/arch

[U-Boot] [PATCH v2 10/11] x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Graeme Russ --- arch/x86/include/asm/cache.h | 35 +++ 1 files changed, 35 insertions(+), 0 deletions(-) create mode 100644 arch/x86/include/asm/cache.h diff --git a/arch/x86/include/asm

[U-Boot] [PATCH v2 06/11] sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Daniel Hellstrom --- arch/sparc/include/asm/cache.h | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 03e8d94..44870e8

[U-Boot] [PATCH v2 09/11] mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Shinya Kuribayashi --- arch/mips/include/asm/cache.h | 36 1 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/cache.h diff --git a/arch/mips

[U-Boot] [PATCH v2 05/11] sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Nobuhiro Iwamatsu --- arch/sh/include/asm/cache.h | 17 + 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 2cfc0a7..6ffab4d

[U-Boot] [PATCH v2 04/11] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Acked-by: Stefan Roese Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Wolfgang Denk Cc: Stefan Roese --- arch/powerpc/include/asm/cache.h |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc

[U-Boot] [PATCH v2 01/11] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Albert ARIBAUD --- arch/arm/include/asm/cache.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index d0518be..eef6a5a 100644

[U-Boot] [PATCH v2 02/11] m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Jason Jin --- arch/m68k/include/asm/cache.h | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 7c84e48..5c9bb30 100644

[U-Boot] [PATCH v2 08/11] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Michal Simek --- arch/microblaze/include/asm/cache.h | 37 +++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/microblaze/include/asm/cache.h diff --git a/arch

[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

nges in v2: - Remove blackfin patches in favor of Mike's import of the Linux kernel cache.h - Remove all Gerrit Change-ID tags Anton Staaf (11): arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment nios2: cache: define

Re: [U-Boot] [PATCH] dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target

On Mon, Oct 17, 2011 at 4:42 AM, Lukasz Majewski wrote: > Define the D-cache line size for S5PC210 UNIVERSAL reference target. > > Signed-off-by: Lukasz Majewski > Signed-off-by: Kyungmin Park Acked-by: Anton Staaf > Cc: Minkyu Kang > --- >  include/configs/s5pc2

Re: [U-Boot] [PATCH] dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target

On Mon, Oct 17, 2011 at 4:42 AM, Lukasz Majewski wrote: > Define the D-cache line size for S5PC110 GONI reference target. > > Signed-off-by: Lukasz Majewski > Signed-off-by: Kyungmin Park Acked-by: Anton Staaf > Cc: Minkyu Kang > --- >  include/configs/s5p_goni.h

Re: [U-Boot] [RESEND PATCH v2] tegra2: Enable data cache

On Fri, Oct 14, 2011 at 9:26 AM, Simon Glass wrote: > Hi Tom & Stephen, > > On Fri, Oct 14, 2011 at 9:02 AM, Stephen Warren wrote: >> Tom Warren wrote at Friday, October 14, 2011 9:56 AM: >>> Stephen Warren wrote at Friday, October 14, 2011 8:04 AM: >>> > Simon Glass wrote at Thursday, October 13

Re: [U-Boot] [PATCH 5/5] mmc: Tegra2: Enable dcache support and bounce unaligned requests.

On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf wrote: > When an unaligned buffer is used for DMA the first and last few > bytes of the buffer would be clobbered by the dcache invalidate > call that is required to make the contents of the buffer visible > to the CPU post DMA.  The

[U-Boot] [PATCH 1/5] mmc: Tegra2: Support DMA restarts at buffer boundaries

the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Stephen Warren --- drivers/mmc/tegra2_mmc.c | 15 +++ 1 files

[U-Boot] [PATCH 5/5] mmc: Tegra2: Enable dcache support and bounce unaligned requests.

the bounce buffer and has a high water mark in memory consumption. Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Stephen Warren --- drivers/mmc/tegra2_mmc.c | 132 - drivers/mmc/tegra2_mmc.h | 14 + 2 files changed, 143 insertions(+), 3

[U-Boot] [PATCH 4/5] mmc: Create dcache flush and invalidate convenience methods

With the enabling of data caches in U-Boot flushing and invalidating MMC buffers will need to be done in all MMC drivers. These utility functions simplify that task slightly. Signed-off-by: Anton Staaf Cc: Andy Fleming --- drivers/mmc/mmc.c | 23 +++ include/mmc.h

[U-Boot] [PATCH 3/5] mmc: Tegra2: Factor out mmc_wait_inhibit functionality

This is a well encapsulated section of mmc_send_cmd, by moving it to it's own function it increases the readability of mmc_send_cmd. Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Stephen Warren --- drivers/mmc/tegra2_mmc.c | 41 ++--- 1 files change

[U-Boot] [PATCH 0/5] mmc: Tegra2: DMA related fixes

this patch. :) Anton Staaf (5): mmc: Tegra2: Support DMA restarts at buffer boundaries mmc: Tegra2: Add data transfer completion timeout mmc: Tegra2: Factor out mmc_wait_inhibit functionality mmc: Create dcache flush and invalidate convenience methods mmc: Tegra2: Enable dcache support by

[U-Boot] [PATCH 2/5] mmc: Tegra2: Add data transfer completion timeout

and we fail out. Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Stephen Warren --- drivers/mmc/tegra2_mmc.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 195f89d..27564b0 100644 --- a/drivers/mmc

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

On Thu, Oct 13, 2011 at 1:36 PM, Mike Frysinger wrote: > On Thursday 13 October 2011 16:03:37 Wolfgang Denk wrote: >> Anton Staaf wrote: >> >              ... I could move it from common.h to a c file that is always >> > >> > built.  Perhaps I could add a c

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

On Thu, Oct 13, 2011 at 1:31 PM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> Turns out I was able to define ARCH_DMA_MINALIGN for all U-Boot >> architectures and use that >> instead of the actual cache line size to gen

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

On Thu, Oct 13, 2011 at 1:03 PM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> Would you be OK with a build warning for the lack of definition of >> CONFIG_SYS_CACHELINE_SIZE like I have now if it only happened >> once per

Re: [U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

On Thu, Oct 13, 2011 at 11:15 AM, Mike Frysinger wrote: > On Thursday 13 October 2011 14:06:41 Anton Staaf wrote: >> On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger wrote: >> > On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote: >> >>  doc/README.arm-caches |  

Re: [U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger wrote: > On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote: >>  doc/README.arm-caches |    2 + > > seems like most of the advice in this is arch independent Agreed. It probably makes sense to change the name of the file. I&

Re: [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures

On Wed, Oct 12, 2011 at 8:47 PM, Kumar Gala wrote: > > On Oct 12, 2011, at 4:01 PM, Anton Staaf wrote: > >> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel.  It is >> used to define the minimum alignement requirement for a DMA buffer.  This >> series

Re: [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE

blackfin/include/asm/config.h > index 53af310..1a8de49 100644 > --- a/arch/blackfin/include/asm/config.h > +++ b/arch/blackfin/include/asm/config.h > @@ -21,6 +21,9 @@ >  # define CONFIG_BFIN_SCRATCH_REG retn >  #endif > > +/* U-Boot wants this config name */ &g

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

This macro is used to allocate cache line size aligned stack buffers for use with DMA hardware. Signed-off-by: Anton Staaf Cc: Lukasz Majewski Cc: Kyungmin Park Cc: Mike Frysinger Cc: Aneesh V Cc: Albert ARIBAUD Cc: Wolfgang Denk --- doc/README.arm-caches |2 + include/common.h

[U-Boot] [PATCH v3 4/6] ext2: Cache line aligned partial sector bounce buffer

not be aligned to the dcache line size. This is a problem when caches are enabled because unaligned cache invalidates are not safe. This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated cache line size aligned bounce buffer. Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc

[U-Boot] [PATCH v3 5/6] mmc: dcache: allocate cache aligned buffers for ext_csd

buffers used for reading the ext_csd data from an MMC device. Signed-off-by: Anton Staaf Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- drivers/mmc/mmc.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index

[U-Boot] [PATCH v3 6/6] part_efi: dcache: allocate cacheline aligned buffers

: Anton Staaf Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- disk/part_efi.c | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 0a513c6..e591724 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c

[U-Boot] [PATCH v3 3/6] mmc: dcache: allocate cache aligned buffer for scr and switch_status

for reading the scr register and switch status values from an MMC device. Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- drivers/mmc/mmc.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers

[U-Boot] [PATCH v3 2/6] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Simon Glass Cc: Mike Frysinger Cc: Albert ARIBAUD --- include/configs/tegra2-common.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 73e0f05

[U-Boot] [PATCH v3 0/6] Add cache line alignment support

size - Remove Gerrit generated Change-Id: tags from commit messages - Add additional buffer alignments for mmc and part_efi code Changes for v3: - Don't set a default value for CONFIG_SYS_CACHELINE_SIZE - Use ARCH_DMA_MINALIGN to align DMA buffers Anton Staaf (6): cache

Re: [U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

On Wed, Oct 12, 2011 at 4:23 PM, Mike Frysinger wrote: > i'm just going to import Blackfin's asm/cache.h from Linux and define > CONFIG_SYS_CACHELINE_SIZE in Blackfin's asm/config.h OK, how would you like to deal with that with respect to this patch set? Would you like to do that and have me remo

Re: [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures

Shoot, I just noticed that I forgot to purge the Gerrit generated Change-Id: tags from the commit messages. If and when I send a v2 series I'll remove these. Thanks, Anton On Wed, Oct 12, 2011 at 2:01 PM, Anton Staaf wrote: > ARCH_DMA_MINALIGN is a new define borrowed from the Linu

[U-Boot] [PATCH 12/12] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition

cache line size then the maximum line size of the architecture is used to align DMA buffers. Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Wolfgang Denk Cc: Stefano Babic Cc: Ilya Yanok Cc: Laurence Withers Change-Id: I6cc14dbc4b8fce3e4820e7b3ad3a06d1f2100152

[U-Boot] [PATCH 01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Albert ARIBAUD Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee --- arch/arm/include/asm/cache.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch

[U-Boot] [PATCH 07/12] avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Reinhard Meyer Change-Id: I5965f64804c3938823be716f45298f093871fe83 --- arch/avr32/include/asm/cache.h | 40 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644

[U-Boot] [PATCH 05/12] sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Nobuhiro Iwamatsu Change-Id: I7dc5fb442b0e9173e9acdaf7acce3014c5b37625 --- arch/sh/include/asm/cache.h | 17 + 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/sh/include/asm/cache.h b

[U-Boot] [PATCH 06/12] sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Daniel Hellstrom Change-Id: If33383ff88e0555204c4ed1534d3961587fdee3a --- arch/sparc/include/asm/cache.h | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/sparc/include/asm/cache.h b

[U-Boot] [PATCH 11/12] x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Graeme Russ Change-Id: Ib4b497910f674904f5fd0d9557a082d661c248bb --- arch/x86/include/asm/cache.h | 35 +++ 1 files changed, 35 insertions(+), 0 deletions(-) create mode 100644 arch/x86

[U-Boot] [PATCH 04/12] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Wolfgang Denk Cc: Stefan Roese Change-Id: I5a007a515ef16e77003aaa74f9295ecc5104aa36 --- arch/powerpc/include/asm/cache.h |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include

[U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Change-Id: Ibdc2483c66c50d698108b790dd204fae38c7cb48 --- arch/blackfin/include/asm/cache.h | 36 1 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 arch/blackfin/include

[U-Boot] [PATCH 02/12] m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Jason Jin Change-Id: Ica2b7459b7a61b521116eb23dc911451b4c2a9a5 --- arch/m68k/include/asm/cache.h | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k

[U-Boot] [PATCH 10/12] mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Shinya Kuribayashi Change-Id: Ia6cc9a950e0452926abf39867a70ec3910fbd1dd --- arch/mips/include/asm/cache.h | 36 1 files changed, 36 insertions(+), 0 deletions(-) create mode 100644

[U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures

t use -Os option if --enable-target-optspace is not set. So Tested-by's would be greatly appreciated. Thanks, Anton Anton Staaf (12): arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment nios2: cac

[U-Boot] [PATCH 09/12] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Michal Simek Change-Id: I8ee488ae0654cebac34f4d65771b4a8edbadf6fd --- arch/microblaze/include/asm/cache.h | 37 +++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644

[U-Boot] [PATCH 03/12] nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Scott McNutt Change-Id: I2982360f1c2ad9e8549d5b9ecdbb423d34b75157 --- arch/nios2/include/asm/cache.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/nios2/include/asm/cache.h b/arch

Re: [U-Boot] [RESEND PATCH v2] tegra2: Enable data cache

On Tue, Oct 11, 2011 at 5:35 PM, Simon Glass wrote: > This enables the data cache on Tegra2 boards. > > As discussed on the list, this is better off in the Tegra2 cpu code than in a > particular vendor directory. We should be safe turning on the cache for all > Tegra2 boards. I don't think it's s

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

On Mon, Oct 10, 2011 at 11:45 AM, Anton Staaf wrote: > On Mon, Oct 10, 2011 at 11:31 AM, Wolfgang Denk wrote: >> Dear Anton Staaf, >> >> In message >> you >> wrote: >>> >>> > When PPC was building again, I tested it on ARM (which I ass

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

On Mon, Oct 10, 2011 at 11:31 AM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> > When PPC was building again, I tested it on ARM (which I assumed was >> > OK, given that this was Anton's primary architecture).

Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

orry, but the rest of what thread ?  i missed that there were issues and was >> wondering why they weren't in the published master branch yet ... > > There are actually three parts to this storey: > > Thisi s the original patch series, which I applied to a local test > branc

Re: [U-Boot] [PATCH v2 0/7] Add cache line alignment support

On Sun, Oct 9, 2011 at 2:22 PM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message <1317763491-7274-1-git-send-email-robot...@chromium.org> you wrote: >> The cache line alignment issue has gone around a couple of times now.  This >> patch set implements all

Re: [U-Boot] [PATCH 1/2] ppc: Include in common.h

On Sun, Oct 9, 2011 at 12:11 PM, Wolfgang Denk wrote: > Dear Anton Staaf, > > In message > you > wrote: >> >> > This is needed for the patch "cache: add default setting for >> > CONFIG_SYS_CACHELINE_SIZE" from Anton Staaf. As cache.h defin

Re: [U-Boot] [PATCH 1/2] ppc: Include in common.h

On Fri, Oct 7, 2011 at 4:05 AM, Stefan Roese wrote: > This is needed for the patch "cache: add default setting for > CONFIG_SYS_CACHELINE_SIZE" from Anton Staaf. As cache.h defines > CONFIG_SYS_CACHELINE_SIZE for PPC targets. > > This will remove the following war

[U-Boot] [PATCH v2 3/7] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc: Tom Warren Cc: Simon Glass Cc: Mike Frysinger Cc: Albert ARIBAUD --- include/configs/tegra2-common.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2

[U-Boot] [PATCH v2 2/7] cache: add default setting for CONFIG_SYS_CACHELINE_SIZE

default is used. Signed-off-by: Anton Staaf Cc: Lukasz Majewski Cc: Kyungmin Park Cc: Mike Frysinger Cc: Aneesh V Cc: Albert ARIBAUD --- Changes for v2: - Add comment describing why we are setting a default cacheline size include/common.h | 14 ++ 1 files changed, 14 insertions

[U-Boot] [PATCH v2 0/7] Add cache line alignment support

ts for mmc and part_efi code Anton Staaf (7): cache: add ALLOC_CACHE_ALIGN_BUFFER macro cache: add default setting for CONFIG_SYS_CACHELINE_SIZE tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra mmc: dcache: allocate cache aligned buffer for scr and switch_status ext2: Cache line align

[U-Boot] [PATCH v2 4/7] mmc: dcache: allocate cache aligned buffer for scr and switch_status

for reading the scr register and switch status values from an MMC device. Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- drivers/mmc/mmc.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers

[U-Boot] [PATCH v2 1/7] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

This macro is used to allocate cache line size aligned stack buffers for use with DMA hardware. Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc: Lukasz Majewski Cc: Kyungmin Park Cc: Mike Frysinger Cc: Aneesh V Cc: Albert ARIBAUD --- doc/README.arm-caches |2 + include

[U-Boot] [PATCH v2 5/7] ext2: Cache line aligned partial sector bounce buffer

not be aligned to the dcache line size. This is a problem when caches are enabled because unaligned cache invalidates are not safe. This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated cache line size aligned bounce buffer. Signed-off-by: Anton Staaf Acked-by: Mike Frysinger Cc

[U-Boot] [PATCH v2 7/7] part_efi: dcache: allocate cacheline aligned buffers

: Anton Staaf Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- disk/part_efi.c | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 1b04c27..1942503 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c

[U-Boot] [PATCH v2 6/7] mmc: dcache: allocate cache aligned buffers for ext_csd

buffers used for reading the ext_csd data from an MMC device. Signed-off-by: Anton Staaf Cc: Lukasz Majewski Cc: Mike Frysinger Cc: Albert ARIBAUD --- drivers/mmc/mmc.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index

Re: [U-Boot] [PATCH 2/5] cache: add default setting for CONFIG_SYS_CACHELINE_SIZE

On Tue, Oct 4, 2011 at 8:14 AM, Mike Frysinger wrote: > On Monday, October 03, 2011 19:54:57 Anton Staaf wrote: >> --- a/include/common.h >> +++ b/include/common.h >> >>  /* >> + * >> + */ > > no comment ? :) Doh, I knew I was forgetting somet

[U-Boot] [PATCH 3/5] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

Signed-off-by: Anton Staaf Cc: Tom Warren Cc: Simon Glass Cc: Mike Frysinger Cc: Albert ARIBAUD Change-Id: I5c4bcfc0bfe59158ff249fe3be6640eec6d3cc76 --- include/configs/tegra2-common.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/tegra2-common.h

[U-Boot] [PATCH 5/5] ext2: Cache line aligned partial sector bounce buffer

not be aligned to the dcache line size. This is a problem when caches are enabled because unaligned cache invalidates are not safe. This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated cache line size aligned bounce buffer. Signed-off-by: Anton Staaf Cc: Lukasz Majewski Cc: Mike

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