On Wed, Oct 12, 2011 at 4:55 PM, Anton Staaf <robot...@chromium.org> wrote:
> The cache line alignment issue has gone around a couple of times now. This
> patch set implements all of the details that we have discussed about the
> implementation of ALLOC_CACHE_ALIGN_BUFFER. It also includes patches that use
> the macro to fix MMC and ext2 buffers, as well as define the
> CONFIG_SYS_CACHELINE_SIZE value for Tegra.
>
> This series now depends on the series to add ARCH_DMA_MINALIGN for all
> architectures and must be applied after that series.
>
> This has been tested on a Seaboard.
This patch set has now been tested with MAKEALL for ARMv7a and
PowerPC. It still
applies cleanly to TOT. Should I resend or is it good as is?
Thanks,
Anton
> Thanks,
> Anton
>
> ---
>
> Changes for v2:
> - Add comment describing why we are setting a default cacheline size
> - Remove Gerrit generated Change-Id: tags from commit messages
> - Add additional buffer alignments for mmc and part_efi code
>
> Changes for v3:
> - Don't set a default value for CONFIG_SYS_CACHELINE_SIZE
> - Use ARCH_DMA_MINALIGN to align DMA buffers
>
> Anton Staaf (6):
> cache: add ALLOC_CACHE_ALIGN_BUFFER macro
> tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
> mmc: dcache: allocate cache aligned buffer for scr and switch_status
> ext2: Cache line aligned partial sector bounce buffer
> mmc: dcache: allocate cache aligned buffers for ext_csd
> part_efi: dcache: allocate cacheline aligned buffers
>
> disk/part_efi.c | 18 ++++++------
> doc/README.arm-caches | 2 +
> drivers/mmc/mmc.c | 14 +++++-----
> fs/ext2/dev.c | 2 +-
> include/common.h | 58
> +++++++++++++++++++++++++++++++++++++++
> include/configs/tegra2-common.h | 2 +
> 6 files changed, 79 insertions(+), 17 deletions(-)
>
> --
> 1.7.3.1
>
>
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