Signed-off-by: Anton Staaf <robot...@chromium.org> Cc: Mike Frysinger <vap...@gentoo.org> Cc: Lukasz Majewski <l.majew...@samsung.com> Cc: Albert ARIBAUD <albert.u.b...@aribaud.net>
Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee --- arch/arm/include/asm/cache.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index d0518be..eef6a5a 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +/* + * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We + * use that value for aligning DMA buffers unless the board config has specified + * an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + #endif /* _ASM_CACHE_H */ -- 1.7.3.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
