Hi Stefano,
On Mon, May 09, 2016 at 09:30:28AM +0200, Stefano Babic wrote:
>On 03/05/2016 05:13, Peng Fan wrote:
>> Correct speed grading info for i.MX6UL
>>
>> Signed-off-by: Peng Fan
>> Cc: Stefano Babic
>> ---
>> arch/arm/cpu/armv7/mx6/soc.c | 15 +++
>> 1 file changed, 15 inser
On Mon, 2016-05-16 at 14:02 +0200, Boris Brezillon wrote:
> Hi Scott,
>
> On Tue, 03 May 2016 00:06:45 -0500
> Scott Wood wrote:
>
> > I usually do syncs when someone complains about needing a sync. Every
> > release
> > seems a bit much. I'll try to do one soon.
>
> Sorry to bother you with
Hi Simon,
On Wed, May 11, 2016 at 10:44 PM, Bin Meng wrote:
> SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu
> and Windows to a SATA drive and boot from there. But till now this
> is broken. The installation either hangs forever or just crashes.
>
> This series fixed a bunch of
Hi,
On Wed, May 18, 2016 at 3:34 AM, wrote:
> Updated to address concerns raised on mailing list.
>
> I won't have time to work on this further for a while; please feel free to
> use / merge anything from the series that
> is acceptable. I'll try to make time again in a month or two to polish
On Wed, May 18, 2016 at 3:25 AM, Timothy Pearson
wrote:
> On 05/17/2016 12:27 AM, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, May 17, 2016 at 10:39 AM, wrote:
>>
>> Description please.
>>
>>> Signed-off-by: Timothy Pearson
>>> ---
>>> arch/arm/cpu/armv7/sunxi/Makefile | 1 +
>>> arch/arm/cp
On Wed, May 18, 2016 at 3:19 AM, Timothy Pearson
wrote:
> On 05/17/2016 12:21 AM, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, May 17, 2016 at 10:38 AM, wrote:
>>> ---
>>> arch/arm/cpu/armv7/psci.S | 1 +
>>> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
>>> arch/arm/cpu/armv7/sunxi/p
Recently Linux is gaining support for efifb on AArch64 and that support actually
tries to make use of the frame buffer address we expose to it via gop.
While this wouldn't be bad in theory, in practice it means a few bad things
1) We expose 16bit frame buffers as 32bit today
2) Linux can't de
We put the system table into our runtime services data section so that
payloads may still access it after exit_boot_services. However, most fields
in it are quite useless once we're in that state, so let's just patch them
out.
With this patch we don't get spurious warnings when running EFI binarie
+Joe
On 16 May 2016 at 23:11, Wenyou Yang wrote:
> Use the right phy_connect() prototype for CONFIGF_DM_ETH.
> Support to get the phy interface from dt and set GMAC_UR.
>
> Signed-off-by: Wenyou Yang
> ---
> This patch is based on the patch set,
> [PATCH 00/18] at91: Convert Ethernet and LCD to
Hi Stephen,
On 17 May 2016 at 10:46, Stephen Warren wrote:
> From: Stephen Warren
>
> This adds a sandbox reset implementation (provider), a test client
> device, instantiates them both from Sandbox's DT, and adds a DM test
> that excercises everything.
>
> Signed-off-by: Stephen Warren
> ---
>
Hi Stephen,
On 17 May 2016 at 10:46, Stephen Warren wrote:
> From: Stephen Warren
>
> A reset controller is a hardware module that controls reset signals that
> affect other hardware modules or chips.
>
> This patch defines a standard API that connects reset clients (i.e. the
> drivers for devic
On 15/05/2016 02:49, Simon Glass wrote:
These are no longer used. The migration is complete. Drop these options.
Signed-off-by: Simon Glass
---
arch/Kconfig | 32
1 file changed, 32 deletions(-)
Acked-by: Angelo Dureghello
On 15/05/2016 02:49, Simon Glass wrote:
Since generic board init is enabled, this is not used. Drop it.
Signed-off-by: Simon Glass
---
arch/m68k/include/asm/u-boot.h | 39 ---
1 file changed, 39 deletions(-)
Acked-by: Angelo Dureghello
___
On 05/17/2016 12:47 PM, Edward L Swarthout wrote:
> From: York Sun [mailto:york@nxp.com]
>> On 05/17/2016 09:35 AM, Edward L Swarthout wrote:
>>> From: Prabhakar Kushwaha:
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+ unsigned int svr, ver;
>>> ...
+ svr = gur_in
From: York Sun [mailto:york@nxp.com]
> On 05/17/2016 09:35 AM, Edward L Swarthout wrote:
> > From: Prabhakar Kushwaha:
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> >> + unsigned int svr, ver;
> > ...
> >> + svr = gur_in32(&gur->svr);
> >> + ver = SVR_SOC_VER(svr);
> >> +
There are two versions of the A83t processor; per the provided
Linux code from Allwinner revisions A and B can be distingushed
by the lower bit of the SRAM ID register. The distinction is
important because revision B requires a SMP bringup workaround.
Signed-off-by: Timothy Pearson
---
arch/arm
The existing stack size was only sufficient for four CPUs.
Keep lower stack range address page alignment intact, and
move the lower stack range address down a page. This has
the effect of expanding the stack range by a single page,
which is enough for four more CPUs.
Signed-off-by: Timothy Pearso
This patch enables non-secure access to all system peripherals
controlled by the STMA, and additionally sets the secure RAM
range to 64k in line with other sunxi devices.
Signed-off-by: Timothy Pearson
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/tzpc.c| 10
This patch adds support for the PSCI cpu_on command on Allwinner
A83t devices. Since cluster 1 is already set up by early init,
the majority of this patch focuses on adding multi-cluster support
to PSCI and A83t power sequencing.
Signed-off-by: Timothy Pearson
---
arch/arm/cpu/armv7/sunxi/psci_
Now that the groundwork has been laid, enable all the pieces to
support PSCI, KVM, and SMP. This has been tested on a mainline
Linux kernel, however that kernel hangs for an unknown reason
during kthread execution even though all cores start normally.
It is currently assumed that this is a non-PSC
Multi-cluster systems require that the CCI be set up if SMP is desired via
PSCI later in the boot process. Start cluster 1 and set up the CCI if
requested by the SoC configuration.
Signed-off-by: Timothy Pearson
---
arch/arm/include/asm/arch-sunxi/prcm.h | 3 ++-
board/sunxi/board.c
Multi-cluster systems require basic initialization of the
cache coherent interconnect to enable SMP via PSCI. Add
the requisite definitions for general use.
Signed-off-by: Timothy Pearson
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 3 +++
arch/arm/include/asm/cci.h | 10
Define number of cores and secure SRAM base in preparation
for A83t SMP / PSCI enablement.
Signed-off-by: Timothy Pearson
---
include/configs/sun8i.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index b9a8731..b239548
Updated to address concerns raised on mailing list.
I won't have time to work on this further for a while; please feel free to use
/ merge anything from the series that
is acceptable. I'll try to make time again in a month or two to polish the
rest of the patches up if needed.
On 05/17/2016 11:55 AM, Michal Simek wrote:
On 17.5.2016 19:30, Stephen Warren wrote:
On 05/17/2016 08:05 AM, Michal Simek wrote:
This is the first attempt how to test qspi.
Detect SPI size. Read it all, random size, erase every block,
write random data with random size and read it back,
erase
On 05/17/2016 12:27 AM, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, May 17, 2016 at 10:39 AM, wrote:
>
> Description please.
>
>> Signed-off-by: Timothy Pearson
>> ---
>> arch/arm/cpu/armv7/sunxi/Makefile | 1 +
>> arch/arm/cpu/armv7/sunxi/tzpc.c| 10 ++
>> arch/arm/include/a
On 05/17/2016 12:21 AM, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, May 17, 2016 at 10:38 AM, wrote:
>> ---
>> arch/arm/cpu/armv7/psci.S | 1 +
>> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
>> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 4 ++--
>> 3 files changed, 5 insertions(+), 4 dele
On 05/17/2016 12:00 PM, Michal Simek wrote:
On 17.5.2016 19:36, Stephen Warren wrote:
On 05/17/2016 11:03 AM, Michal Simek wrote:
On 17.5.2016 19:00, Stephen Warren wrote:
On 05/17/2016 10:56 AM, Michal Simek wrote:
Hi Stephen,
On 17.5.2016 18:50, Stephen Warren wrote:
On 05/17/2016 07:57 A
On 17.5.2016 19:36, Stephen Warren wrote:
> On 05/17/2016 11:03 AM, Michal Simek wrote:
>> On 17.5.2016 19:00, Stephen Warren wrote:
>>> On 05/17/2016 10:56 AM, Michal Simek wrote:
Hi Stephen,
On 17.5.2016 18:50, Stephen Warren wrote:
> On 05/17/2016 07:57 AM, Michal Simek wrote:
On 17.5.2016 19:30, Stephen Warren wrote:
> On 05/17/2016 08:05 AM, Michal Simek wrote:
>> This is the first attempt how to test qspi.
>> Detect SPI size. Read it all, random size, erase every block,
>> write random data with random size and read it back,
>> erase the whole qspi and at the end load
Hi Tom,
This includes a refinement of the GPIO interface, soft SPI fixes,
driver model block-device support (and a legacy driver for
non-driver-model code) and a few other things. The changes are fairly
major so I'd like to get the maximum possible test window.
The following changes since commit
On 05/17/2016 11:03 AM, Michal Simek wrote:
On 17.5.2016 19:00, Stephen Warren wrote:
On 05/17/2016 10:56 AM, Michal Simek wrote:
Hi Stephen,
On 17.5.2016 18:50, Stephen Warren wrote:
On 05/17/2016 07:57 AM, Michal Simek wrote:
If timeout happen it should be reported as fault.
Presumably i
Hello,
I'm looking for some help fixing a possible issue on AR9331 platforms
covered by the AR71xx target. In uBoot we're getting nothing but framing
errors over serial. Once Linux initializes the port. everything works
fine. Digging in the code, I've been able to find that the Linux driver
for
Trying to enumerate a bluetooth dongle.
The connected bluetooth dongle has 2 interfaces. Pls see the bottom of the
mail for device and config descriptors.
We are using interface 0 having 3 end points - Interrupt IN, Bulk OUT and
Bulk In.
For enumeration we are still using uboot's "usb_new_device()
On 05/17/2016 08:05 AM, Michal Simek wrote:
This is the first attempt how to test qspi.
Detect SPI size. Read it all, random size, erase every block,
write random data with random size and read it back,
erase the whole qspi and at the end load kernel image via tftp
and save it to memory.
I don'
From: Prabhakar Kushwaha:
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> unsigned int cpu;
> + unsigned int svr, ver;
> const u8 core_cplx_pll[8] = {
...
> - FSL_CHASSIS2_RCWSR0_MEM_PLL_RA
On 17.5.2016 19:00, Stephen Warren wrote:
> On 05/17/2016 10:56 AM, Michal Simek wrote:
>> Hi Stephen,
>>
>> On 17.5.2016 18:50, Stephen Warren wrote:
>>> On 05/17/2016 07:57 AM, Michal Simek wrote:
If timeout happen it should be reported as fault.
>>>
>>> Presumably if a timeout occurs, the e
On 05/17/2016 10:56 AM, Michal Simek wrote:
Hi Stephen,
On 17.5.2016 18:50, Stephen Warren wrote:
On 05/17/2016 07:57 AM, Michal Simek wrote:
If timeout happen it should be reported as fault.
Presumably if a timeout occurs, the expected text does not appear, i.e.
the existing assert fails an
Support loading FIT in SPL for RAM bootmode.
CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
in memory.
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
---
Changes in v2:
- Fix empty line
- Fix addr name and remove SPL_LOAD_FIT macro
common/spl/spl.c | 45 +
Hi Stephen,
On 17.5.2016 18:50, Stephen Warren wrote:
> On 05/17/2016 07:57 AM, Michal Simek wrote:
>> If timeout happen it should be reported as fault.
>
> Presumably if a timeout occurs, the expected text does not appear, i.e.
> the existing assert fails anyway?
>
> Anyway, it's useful to poin
On 05/17/2016 09:35 AM, Edward L Swarthout wrote:
> From: Prabhakar Kushwaha:
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
>> unsigned int cpu;
>> +unsigned int svr, ver;
>> const u8 core_cplx_pll[8] = {
> ..
On 05/17/2016 07:57 AM, Michal Simek wrote:
If timeout happen it should be reported as fault.
Presumably if a timeout occurs, the expected text does not appear, i.e.
the existing assert fails anyway?
Anyway, it's useful to point out problems explicitly, so,
Acked-by: Stephen Warren
From: Stephen Warren
A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.
This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers.
From: Stephen Warren
This adds a sandbox reset implementation (provider), a test client
device, instantiates them both from Sandbox's DT, and adds a DM test
that excercises everything.
Signed-off-by: Stephen Warren
---
arch/sandbox/dts/test.dts | 11
arch/sandbox/include/asm/res
On 03/14/2016 11:45 PM, Yuan Yao wrote:
> From: Yuan Yao
>
> The address value and size value get from dts "reg" property have type
> of u64 on arm64.
> If we assign those values to "u32" variables, driver can't work correctly.
> Converting the type of those variables to fdt_xxx_t.
>
> Signed-of
On 05/05/2016 12:29 PM, York Sun wrote:
> On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
>> Optimize DDR timing for good margins to support new Transcend
>> and Apacer DDR4 UDIMM besides current Micron UDIMM.
>>
>> Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
>> following UDIMM on LS2080
On 03/14/2016 11:44 PM, Yuan Yao wrote:
> From: Yuan Yao
>
> There is the spansion S25FS-S family flash: s25fs256s1
> on LS2080QDS QSPI.
>
> Yuan Yao (5):
> spi: fsl_qspi: Fix issues on arm64
> spi: fsl_qspi: Assign AMBA mem according CS num in dts
> spi: fsl_qspi: Enable Spansion S25FS-S
On 04/26/2016 06:55 PM, Gong Qianyu wrote:
> There is no MODE_FAT but MODE_FS. Fix it.
Actually this macro existed before being renamed by commit
205b4f33cfe58268df7d433f2da515fe660afd9c. No need to resend the patch. I will
update the command message when merging.
York
>
> Signed-off-by: Gong Q
Hi Paul,
On 17 May 2016 at 09:58, Paul Burton wrote:
> On Tue, May 17, 2016 at 09:54:21AM -0600, Simon Glass wrote:
>> > >> > diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> > >> > index 28da9dd..e58e6aa 100644
>> > >> > --- a/drivers/serial/ns16550.c
>> > >> > +++ b/drivers/s
On Tue, May 17, 2016 at 09:54:21AM -0600, Simon Glass wrote:
> > >> > diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> > >> > index 28da9dd..e58e6aa 100644
> > >> > --- a/drivers/serial/ns16550.c
> > >> > +++ b/drivers/serial/ns16550.c
> > >> > @@ -100,7 +100,11 @@ static void ns1
Hi Tom,
please pull from u-boot-imx, thanks !
The following changes since commit aeaec0e682f45b9e0c62c522fafea353931f73ed:
Prepare v2016.05 (2016-05-16 10:40:32 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-imx.git master
for you to fetch changes up to 291000
Hi Daniel,
On 17 May 2016 at 09:51, Daniel Schwierzeck
wrote:
>
> 2016-05-17 14:48 GMT+02:00 Paul Burton :
> > On Tue, May 17, 2016 at 06:11:22AM -0600, Simon Glass wrote:
> >> Hi Paul,
> >>
> >> On 16 May 2016 at 11:44, Paul Burton wrote:
> >> > If the UART is to be accessed using I/O port acce
2016-05-17 14:48 GMT+02:00 Paul Burton :
> On Tue, May 17, 2016 at 06:11:22AM -0600, Simon Glass wrote:
>> Hi Paul,
>>
>> On 16 May 2016 at 11:44, Paul Burton wrote:
>> > If the UART is to be accessed using I/O port accessors (inb & outb) then
>> > using map_physmem doesn't make sense, since it op
On 05/16/2016 08:28 PM, Yunhui Cui wrote:
> Hi York,
>
> I think you can move your code into timer_init() in cpu.c and follow the
> example of cltbenr.
> [Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig
> bootup on ls2080ardb, timer_init() cannot be called ...
>
On 05/17/2016 12:37 AM, Masahiro Yamada wrote:
> __asm_dcache_all can directly return to the caller of
> __asm_{flush,invalidate}_dcache_all.
>
> We do not have to waste x16 register here.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> arch/arm/cpu/armv8/cache.S | 10 ++
> 1 file changed
On 04/01/2016 12:09 AM, Sumit Garg wrote:
> For mpc85xx SoCs, the core begins execution from address 0xFFFC.
> In non-secure boot scenario from NAND, this address will map to CPC
> configured as SRAM. But in case of secure boot, this default address
> always maps to IBR (Internal Boot ROM).
> T
> From: Fabio Estevam [mailto:fabio.este...@nxp.com]
> Sent: Tuesday, May 17, 2016 10:52 AM
> To: sba...@denx.de
> Cc: Daiane Angolini ; u-boot@lists.denx.de; Fabio
> Estevam
> Subject: [PATCH v2] pico-imx6ul: Select CONFIG_HUSH_PARSER option
>
> Select CONFIG_HUSH_PARSER option in order to fix t
Hello Michal,
I have a minor comment.
On Thu, Apr 28, 2016 at 11:43 AM, Michal Simek wrote:
> Support loading FIT in SPL for RAM bootmode.
> CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
> in memory.
>
> Signed-off-by: Michal Simek
> ---
>
[...]
> + debug("%s: sec
More partitions are handled.
Save information about saved file to structure.
Also use fs_generic commands to handle files.
Support fat, ext2 and ext4 filesystems.
Signed-off-by: Michal Simek
---
Code for work with partitions and FS is quite generic that the same
stuff can be used for others(USB,
Select CONFIG_HUSH_PARSER option in order to fix the following
problem:
Unknown command 'if' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'else' - try 'help'
Unknown command 'fi' - try 'help'
Reported-by: Daiane Angolini
Signed-off-by: Fabio Estevam
---
Changes since v1:
- R
This is the first attempt how to test qspi.
Detect SPI size. Read it all, random size, erase every block,
write random data with random size and read it back,
erase the whole qspi and at the end load kernel image via tftp
and save it to memory.
Signed-off-by: Michal Simek
---
test/py/tests/test
If timeout happen it should be reported as fault.
Signed-off-by: Michal Simek
---
test/py/tests/test_net.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 4f4a876c1335..833a8fd5b3e3 100644
--- a/test/py/tests/test_net.py
+++ b/
Select CONFIG_HUSH_PARSER option in order to fix the following
problem:
Unknown command 'if' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'else' - try 'help'
Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.
Signed-off-by: Michal Simek
---
Tests are running on Sandbox and this support requires FPGA co
On 5/17/2016 4:56 PM, Tom Rini wrote:
On Tue, May 17, 2016 at 09:49:53AM +0530, Lokesh Vutla wrote:
On 5/17/2016 6:11 AM, Tom Rini wrote:
On Mon, May 16, 2016 at 11:47:29AM +0530, Lokesh Vutla wrote:
Different AM335x based platforms have different serial consoles. As serial
console is Kco
Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.
Signed-off-by: Michal Simek
---
common/image-fit.c| 4 +++
common/image.c| 1 +
doc/uImage.FIT/multi-with-fpga.its| 67 +++
doc/uImage.FIT/sourc
Add support for the zynqmpimage to mkimage.
Only basic functionality is supported without encryption and register
initialization with one partition which is filled by U-Boot SPL.
For more detail information look at Xilinx ZynqMP TRM.
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
---
Chan
On Tue, May 17, 2016 at 06:11:22AM -0600, Simon Glass wrote:
> Hi Paul,
>
> On 16 May 2016 at 11:44, Paul Burton wrote:
> > If the UART is to be accessed using I/O port accessors (inb & outb) then
> > using map_physmem doesn't make sense, since it operates in a different
> > memory space. Remove
Trivial patch.
Signed-off-by: Michal Simek
---
drivers/fpga/fpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index d94eb5cc25c4..7e2f3e17a764 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -120,7 +120,7 @@ static
Hello Tom,
please pull from u-boot-i2c.git master
There is a compile fix from Mario, also DM support for fsl_i2c,
DM support for TI PCA954X muxes from Michal, a check for the enable
status register in the designware i2c driver from Stefan and a fix
for the mvtwsi driver, which now does not need
On Sun, 15 May 2016, Robert P. J. Day wrote:
>
> i'm feeling particularly stupid today in not understanding some of
> the things i'm running across. just tripped over this in
> board/spear/common/Makefile:
>
> ...
> ifdef CONFIG_SPL_BUILD
> # necessary to create built-in.o
> obj- := __du
Hi Michal,
On 17 May 2016 at 00:27, Michal Simek wrote:
> Add support for the zynqmpimage to mkimage.
> Only basic functionality is supported without encryption and register
> initialization with one partition which is filled by U-Boot SPL.
> For more detail information look at Xilinx ZynqMP TRM.
Hi Paul,
On 16 May 2016 at 11:44, Paul Burton wrote:
> If the UART is to be accessed using I/O port accessors (inb & outb) then
> using map_physmem doesn't make sense, since it operates in a different
> memory space. Remove the call to map_physmem when
> CONFIG_SYS_NS16550_PORT_MAPPED is defined,
On 16 May 2016 at 11:44, Paul Burton wrote:
> Provide some documentation for the fields of struct of_bus, for
> consistency with that provided for the new match field.
>
> Signed-off-by: Paul Burton
> ---
>
> Changes in v2:
> - New patch.
>
> common/fdt_support.c | 19 +++
> 1 fi
Hi Paul,
On 16 May 2016 at 11:44, Paul Burton wrote:
> Support ISA busses in much the same way as Linux does. This allows for
> ISA bus addresses to be translated, and only if CONFIG_OF_ISA_BUS is
> selected in order to avoid including the code in builds which won't need
> it.
>
> Signed-off-by:
ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.
Signed-off-by: Michal Simek
---
configs/xilinx_zynqmp_ep_defconfig | 2 ++
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 2 ++
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 2 ++
configs
Add missing u-boot,dm-pre-reloc to get IPs initialized.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c6ba8728075a..619450e1ba92 100644
--- a/arch/arm/dts/zynqmp.dtsi
++
Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.
2016-05-17 12:56 GMT+02:00 Paul Burton :
> This series allows MIPS64 builds for Malta boards, which can be used
> either on real Malta boards with a MIPS64 CPU or in QEMU. It prepares by
> moving CONFIG_SYS_TEXT_BASE to Kconfig and fixing some 64 bit build
> issues that affect the ethernet driver,
On Tue, May 17, 2016 at 09:49:53AM +0530, Lokesh Vutla wrote:
>
>
> On 5/17/2016 6:11 AM, Tom Rini wrote:
> >On Mon, May 16, 2016 at 11:47:29AM +0530, Lokesh Vutla wrote:
> >
> >>Different AM335x based platforms have different serial consoles. As serial
> >>console is Kconfig option a separate de
Hi Marek,
2016-05-16 23:46 GMT+09:00 Marek Vasut :
>> delete mode 100644 drivers/usb/host/xhci-uniphier.c
>>
> CCing Roger, so he can check this series. I will review it later today
> or tomorrow.
>
01-03 are probably OK, but 04- might have conflicts with
Roger's work.
Maybe we should take ou
2016-05-17 8:40 GMT+02:00 Paul Burton :
> On Mon, May 16, 2016 at 08:56:32PM +0200, Daniel Schwierzeck wrote:
>> > diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
>> > new file mode 100644
>> > index 000..1dba606
>> > --- /dev/null
>> > +++ b/arch/mips/dts/mti,malta.dts
>
Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.
Signed-off-by: Paul Burton
---
drivers/net/pcnet.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcne
When building for MIPS64 and providing a pointer to _ACAST32_,
optionally via CPHYSADDR or one of the CKSEGxADDR macros, the cast
directly to a 32 bit int leads to compilation warnings such as the
following:
In file included from ./arch/mips/include/asm/io.h:17:0,
from drivers
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton
---
arch/mips/Kconfig | 3 +++
board/imgtec/m
Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board
Kconfig files matching what was present in their config headers. This
will make it cleaner to conditionalise the value for Malta based on 32
vs 64 bit builds.
Signed-off-by: Paul Burton
---
Kconfig |
This series allows MIPS64 builds for Malta boards, which can be used
either on real Malta boards with a MIPS64 CPU or in QEMU. It prepares by
moving CONFIG_SYS_TEXT_BASE to Kconfig and fixing some 64 bit build
issues that affect the ethernet driver, then allows the builds for the
Malta board.
This
When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in computing
the bus number.
The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A given
bus num
2016-05-13 21:23 GMT+09:00 Marek Vasut :
> On 05/13/2016 02:17 PM, Roger Quadros wrote:
>> DWC3 can be used in host only or gadget only mode.
>>
>> Signed-off-by: Roger Quadros
>> ---
>> drivers/usb/dwc3/Kconfig | 9 +
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/
Hi.
2016-05-13 21:17 GMT+09:00 Roger Quadros :
> DWC3 can be used in host only or gadget only mode.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/usb/dwc3/Kconfig | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kco
On 17/05/16 11:57, Masahiro Yamada wrote:
> Hi Roger,
>
>
> 2016-05-17 17:20 GMT+09:00 Roger Quadros :
>> Hi Masahiro,
>>
>> On 16/05/16 15:51, Masahiro Yamada wrote:
>>> Synopsys DWC3 IP generally works with an SoC-specific glue layer.
>>> DT binding for that is like this:
>>>
>>> usb3_glue {
> On 16.05.16 07:28, Huan Wang wrote:
> >> On 13.05.16 10:40, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to kernel.
> >>>
> >>> The architecture information will be got through checking FIT image,
> >>> then U-
Hi Roger,
2016-05-17 17:20 GMT+09:00 Roger Quadros :
> Hi Masahiro,
>
> On 16/05/16 15:51, Masahiro Yamada wrote:
>> Synopsys DWC3 IP generally works with an SoC-specific glue layer.
>> DT binding for that is like this:
>>
>> usb3_glue {
>> compatible = "foo,dwc3";
>> ...
>>
From: Alexander Graf
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.
This patch makes use of that features and sets GICC and G
Hi Masahiro,
On 16/05/16 15:51, Masahiro Yamada wrote:
> Synopsys DWC3 IP generally works with an SoC-specific glue layer.
> DT binding for that is like this:
>
> usb3_glue {
> compatible = "foo,dwc3";
> ...
>
> usb3 {
> compatible = "snps,dwc3";
On Mon, 16 May 2016 22:16:35 +0900,
Simon Glass wrote:
>
> Hi,
>
> On 16 May 2016 at 00:18, Yoshinori Sato wrote:
> > On Sun, 15 May 2016 08:19:39 +0900,
> > Simon Glass wrote:
> >>
> >> Hi,
> >>
> >> On 18 October 2015 at 10:19, Masahiro Yamada
> >> wrote:
> >> > 2015-10-19 0:54 GMT+09:00 Tom
Masahiro Yamada (3):
arm64: optimize __asm_{flush,invalidate}_dcache_all
arm64: fix comment "flush & invalidate"
arm64: rename __asm_flush_dcache_level to __asm_dcache_level
arch/arm/cpu/armv8/cache.S | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
--
We should say "clean & invalidate", or simply "flush".
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv8/cache.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 1c71a2f..6aaecf3 100644
--- a/arch/arm/cpu/a
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv8/cache.S | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/
Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv8/cache.S | 12 ++--
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