On Fri, 2016-03-25 at 01:10 +0100, Karsten Merker wrote:
> > - if ((version & 0x) == 0x1650)
> > + /*
> > + * Ideally this would be a switch case, bit we do not know exactly
>
> s/bit/but/
Other than that, both patches:
Acked-by: Ian Campbell
On Fri, 25 Mar 2016 07:37:25 +0100, Albert ARIBAUD
wrote:
> Hello Tom,
> That way,
>
> 0) U-Boot gets the stable and controlled AEABI support you want;
>
> 1) GCC keeps its somewhat stable but uncontrolled internal "generated
>code / libgcc" interface;
>
> 2) U-Boot won't interfere with no
Hello Sergey,
On Thu, 24 Mar 2016 18:37:52 -0700 (PDT), Sergey Kubushyn
wrote:
> On Thu, 24 Mar 2016, Tom Rini wrote:
> U-Boot is a standalone program not supposed to coexist with any external
> applications i.e. it is totally self-sufficient, not living in some kind of
> system environment so i
Hello Tom,
On Thu, 24 Mar 2016 20:49:42 -0400, Tom Rini wrote:
> On Thu, Mar 24, 2016 at 08:50:03AM +0100, Albert ARIBAUD wrote:
> > Hello Tom,
> >
> > On Wed, 23 Mar 2016 17:36:17 -0400, Tom Rini wrote:
> > > On Wed, Mar 23, 2016 at 06:08:45PM +0100, Albert ARIBAUD wrote:
> > > > Hello Tom,
>
Support Driver Model for fsl esdhc driver.
1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
- Introduce fsl_esdhc_init to be common usage for DM and non-DM
- Introduce fsl_esdhc_cfg_to_priv to build the bridge for non
> -Original Message-
> From: york sun
> Sent: Thursday, March 24, 2016 11:08 PM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: joe.hershber...@gmail.com
> Subject: Re: [PATCH] driver: net: ldpaa_eth: return number of buffer seeded
>
> On 03/18/2016 03:45 AM, Prabhakar Kushwaha w
This adds an explanation of which Raspberry Pi models each target option
supports.
Signed-off-by: Stephen Warren
---
v2: Enhance the Kconfig description to contain complete details re: how to
run rpi_2_defconfig on a Raspberry Pi 3.
---
arch/arm/mach-bcm283x/Kconfig | 28
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot fo
To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the en
Signed-off-by: Stephen Warren
---
v2: No change.
This series depends on:
* My series beginning with "ARM: bcm283x: don't always define
CONFIG_BCM2835"
* My patch "serial: add BCM283x mini UART driver".
* Alexander Graf's arm64 page table/cache series starting with
"arm64: Add 32bit arm compa
This allows U-Boot to known the name of the board.
The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should
On 03/16/2016 08:41 AM, Alexander Graf wrote:
This patch set converts the Raspberry Pi 2 system to properly make use of
the caches available in it.
Because we're running in HYP mode, we first need to teach U-Boot how to
make use of HYP registers and the LPAE page layout which is mandated by
hard
On 03/24/2016 03:31 AM, Alexander Graf wrote:
The bcm2835 frame buffer is in RAM, so we can easily map it as cached and gain
all the glorious performance boost that brings with it.
Tested-by: Stephen Warren
Acked-by: Stephen Warren
___
U-Boot mailin
On 03/23/2016 10:54 PM, Stephen Warren wrote:
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry
On Thu, 24 Mar 2016, Tom Rini wrote:
On Thu, Mar 24, 2016 at 08:50:03AM +0100, Albert ARIBAUD wrote:
Hello Tom,
On Wed, 23 Mar 2016 17:36:17 -0400, Tom Rini wrote:
On Wed, Mar 23, 2016 at 06:08:45PM +0100, Albert ARIBAUD wrote:
Hello Tom,
On Wed, 23 Mar 2016 09:22:38 -0400, Tom Rini wrote
On Thu, Mar 24, 2016 at 08:50:03AM +0100, Albert ARIBAUD wrote:
> Hello Tom,
>
> On Wed, 23 Mar 2016 17:36:17 -0400, Tom Rini wrote:
> > On Wed, Mar 23, 2016 at 06:08:45PM +0100, Albert ARIBAUD wrote:
> > > Hello Tom,
> > >
> > > On Wed, 23 Mar 2016 09:22:38 -0400, Tom Rini wrote:
> > > > On We
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 08:08 PM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 07:43 PM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:54 AM, Serge
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/board.c | 20
1 file changed, 16 insertions(+),
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/cpu_info.c | 24 +++-
1 file changed
Hi All,
For details see:
https://bugzilla.redhat.com/show_bug.cgi?id=1318788
We could really use a hand from someone who knows the
cache code flushing code well and can check if the
generated assembly works as intended.
The preferred method of communication for this is
through bugzilla.
Thank
On 03/24/2016 08:08 PM, Sergey Kubushyn wrote:
> On Thu, 24 Mar 2016, Marek Vasut wrote:
>
>> On 03/24/2016 07:43 PM, Sergey Kubushyn wrote:
>>> On Thu, 24 Mar 2016, Sergey Kubushyn wrote:
>>>
On Thu, 24 Mar 2016, Marek Vasut wrote:
> On 03/24/2016 12:54 AM, Sergey Kubushyn wrote:
>
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 07:43 PM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:54 AM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:47 AM, Serg
On 03/24/2016 07:43 PM, Sergey Kubushyn wrote:
> On Thu, 24 Mar 2016, Sergey Kubushyn wrote:
>
>> On Thu, 24 Mar 2016, Marek Vasut wrote:
>>
>>> On 03/24/2016 12:54 AM, Sergey Kubushyn wrote:
>>> > On Thu, 24 Mar 2016, Marek Vasut wrote:
>>> > > > On 03/24/2016 12:47 AM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:54 AM, Sergey Kubushyn wrote:
> On Thu, 24 Mar 2016, Marek Vasut wrote:
>
> > On 03/24/2016 12:47 AM, Sergey Kubushyn wrote:
> > > On Thu, 24 Mar 2016, Marek Vasut wrote:
> > >
> > > >
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:54 AM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:47 AM, Sergey Kubushyn wrote:
On Thu, 24 Mar 2016, Marek Vasut wrote:
On 03/24/2016 12:08 AM, Tom Rini wrote:
On Wed, Mar 23, 2016 at 04:02:07PM
On 03/24/2016 03:30 AM, Nicolae Rosia wrote:
Hello,
I'm trying to write the contents of a variable to a file using ext4write
but it requires a memory address as input.
Is there an easy way to get the contents of a variable to a particular mem
address?
You weren't completely specific about you
On 03/18/2016 03:45 AM, Prabhakar Kushwaha wrote:
> if buffer < 7, return number of buffer seeded to QBMAN.
>
> Signed-off-by: Prabhakar Kushwaha
> Reported-by: Jose Rivera
> ---
> drivers/net/ldpaa_eth/ldpaa_eth.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/driver
On Tue, Mar 22, 2016 at 05:50:41PM -0700, Steve Rae wrote:
> This reverts commit 9e4b510d40310bf46e09f4edd0a0b6356213df47.
>
> Signed-off-by: Steve Rae
> ---
> As discussed on the mailing list, this change breaks the download portion
> of fastboot by causing the server (the device running U-Boot
On Tue, Mar 22, 2016 at 11:37 PM, Stephen Warren wrote:
> On 03/22/2016 01:59 PM, Semen Protsenko wrote:
>>
>> From: Sam Protsenko
>>
>> The description was borrowed from kernel. "tristate" type was changed
>> to "bool" (I believe we don't support modules for u-boot yet, right?).
>> CONFIG_USB_GA
Hello,
I'm trying to write the contents of a variable to a file using ext4write
but it requires a memory address as input.
Is there an easy way to get the contents of a variable to a particular mem
address?
Best regards,
Nicolae
___
U-Boot mailing list
Hello, I was attempting to create a custom u-boot command. But I am not
able to get the
"run_command" or "cli_simple_run_command" to work.
I`m building u-boot: am335x_boneblack_defconfig
Attempting to use the "run_command" function results in:
| common/built-in.o: In function `run_command':
|
/h
CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig where it makes sense.
Signed-off-by: Denis Bakhvalov
Reported-by: Denis Bakhvalov
Cc: Marek Vasut
Acked-by: Marek Vasut
---
Changes for v2:
- Diff was generated from u-boot-socfpga
configs/socfpga_arr
Add some basic clarification that the dev.key file generated by OpenSSL
contains both the public and private key, and further highlight that
the certificate generated here contains the public key only.
Signed-off-by: Andreas Dannenberg
---
doc/uImage.FIT/signature.txt | 8
1 file change
Different sections in the document suggest flattened image tree blob
files have a file name extension of .itb. Fix the list of file extensions
to reflect that.
Signed-off-by: Andreas Dannenberg
---
doc/uImage.FIT/source_file_format.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 03/24/2016 01:17 AM, Vincent wrote:
> Hi,
> I started to port my kernel to the secure world on a LS1021a board, so
> I started to read the reference manual on the CSU component. In Table
> 9.8, we can see that
>
> - Debug EPU is CSL47[24:16]
> - DDDI is CSL48[24:16]
> - Debug GDI is CSL48[8:0]
On 03/24/2016 09:45 AM, Denis Bakhvalov wrote:
> CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
> and placed in socfpga_*_defconfig where it makes sense.
When I read the commit message and I pretend to have no experience with
socfpga, the following question comes to mind:
And why exactly
On Thu, Mar 24, 2016 at 7:31 AM, Lokesh Vutla wrote:
>
>
> On Thursday 24 March 2016 12:13 AM, Semen Protsenko wrote:
>>
>> Hi All,
>>
>> This series reverts recently added patches that break fastboot command.
>> I propose to keep it this way until issue is found and fixed.
>
> Let's get this fixe
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c |
Masahiro Yamada (10):
serial: uniphier: use devm_get_addr() to get base address
clk: uniphier: use devm_get_addr() to get base address
i2c: uniphier: use devm_get_addr() to get base address
gpio: uniphier: use devm_get_addr() to get base address
mmc: uniphier: use devm_get_addr() to ge
The core part of the UniPhier pinctrl driver needs to support a new
quirk for upcoming UniPhier ARMv8 SoCs. This often happens because
pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones. Having
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/Kconfig | 6 ++
drivers/pinctrl/uniphier/Makefile| 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 113
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-core.c | 9 +++---
Upcoming new pinctrl drivers of PH1-LD11/LD20 support input signal
gating for each pin. (While, existing ones only support it per pin
group.) This commit prepares the core part for that.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 28 +
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/gpio/gpio-uniphier.c | 8 +++-
1 file c
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/mmc/uniphier-sd.c | 9 ++---
1 file cha
The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/Kconfig | 4 ++--
drivers/pinctrl/uniphier/pinctrl-uniphier-ld2
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/i2c/i2c-uniphier-f.c | 12 +---
dri
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada
---
drivers/serial/serial_uniphier.c | 8 +---
1 fi
This command would be useful to update U-Boot images in SRAM.
Signed-off-by: Masahiro Yamada
---
include/configs/uniphier.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index da80c00..059b034 100644
--- a/include/configs/uniphie
Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image")
claimed that u-boot-with-spl.bin would be useful in its commit log,
but it was not available because the commit missed to define
CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined
either (see include/config_fallbacks.
From: Graham Moore
Read Denali hardware revision number and use it to
calculate max_banks, The encoding of max_banks changed
in Denali revision 5.1.
[ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ]
Signed-off-by: Graham Moore
[Brian: parentheses around macro arg]
Signed-off-by: Bri
Hi,
On Thu, Mar 24, 2016 at 2:46 PM, Michael Haas wrote:
>
> This patch is required to get reliable 1000BASE-T operation on some
> boards using the RTL8211C(L) PHY.
>
> Following discussions on v2 of this patch, I have removed the incorrect
> check for the RTL8211C(L). Affected boards now have to
Hi Michael,
On 24-03-16 07:46, Michael Haas wrote:
This patch is required to get reliable 1000BASE-T operation on some
boards using the RTL8211C(L) PHY.
Following discussions on v2 of this patch, I have removed the incorrect
check for the RTL8211C(L). Affected boards now have to define
CONFIG_
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actua
Hi Lokesh,
>
>
> On Thursday 24 March 2016 02:11 PM, Lukasz Majewski wrote:
> > Hi Lokesh,
> >
> >> dma_addr_t holds any valid DMA address. If the DMA API only uses
> >> 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus
> >> addresses, e.g., PCI BARs, may be wider than 32 bits, but d
Hi Tom,
please pull the following patches from the marvell git
repository. I plan to send some other patches still under
review a bit later - perhaps in a week or. As I'm off in
Easter vacation starting tomorrow.
Thanks,
Stefan
The following changes since commit d085ecd61b9956cda0d37b89b5c538f54
On Thu, Mar 24, 2016 at 10:13:35AM +0100, Stefan Roese wrote:
> On 04.01.2016 12:25, Marek Vasut wrote:
> > On Monday, January 04, 2016 at 04:02:26 AM, Phil Sutter wrote:
> >> Hi,
> >>
> >> On Mon, Jan 04, 2016 at 12:47:37AM +0100, Marek Vasut wrote:
> >>> On Monday, January 04, 2016 at 12:38:07 AM
The bcm2835 frame buffer is in RAM, so we can easily map it as cached and gain
all the glorious performance boost that brings with it.
Signed-off-by: Alexander Graf
---
v2 -> v3:
- Fix align parameters
- Fix whitespace
v3 -> v4:
- Align start of fb as well to align with segments
- Al
Hi Kevin,
On 01.09.2015 14:52, Stefan Roese wrote:
Hi Kevin,
(Added Luka to Cc, as the Marvell / MVEBU custodian)
On 31.08.2015 22:30, Kevin Smith wrote:
On some processors such as Armada 38x, if the hardware-
configured boot mode fails, the CPU falls back to booting over
UART. When this hap
On 04.01.2016 12:25, Marek Vasut wrote:
On Monday, January 04, 2016 at 04:02:26 AM, Phil Sutter wrote:
Hi,
On Mon, Jan 04, 2016 at 12:47:37AM +0100, Marek Vasut wrote:
On Monday, January 04, 2016 at 12:38:07 AM, Phil Sutter wrote:
The bit which really was missing is the USB mode setting I smu
On 16.02.2016 22:28, Kevin Smith wrote:
Add command-line specification of xmodem timeout. If the binary
header needs to take a while to do something (e.g. DDR ECC
scrubbing), the xmodem transfer can time out. Add a configurable
xmodem block timeout to allow transfers with slow binary headers
to
On Thursday 24 March 2016 02:11 PM, Lukasz Majewski wrote:
> Hi Lokesh,
>
>> dma_addr_t holds any valid DMA address. If the DMA API only uses
>> 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus
>> addresses, e.g., PCI BARs, may be wider than 32 bits, but drivers do
>> memory-mapped I
On 16.02.2016 22:28, Kevin Smith wrote:
Usage text was getting unwieldy and somewhat incorrect. The
usage summary implied that some options were mutually exclusive
(e.g. -q or -s). Clean up the summary to just include the
important ones, and include a generic "[OPTIONS]" instead.
Signed-off-by
On 15.02.2016 19:13, Andreas Färber wrote:
It has been superseded in kwbimage.cfg in favor of an SPL in commit
9e30b31d20f0b793465d07f056b3d9885f578c0d (arm: mvebu: db-88f6820: Add
SPL support with DDR init code). Found via code review.
Cc: Stefan Roese
Signed-off-by: Andreas Färber
Applied
> Am 24.03.2016 um 03:05 schrieb Stephen Warren :
>
>> On 03/23/2016 06:27 PM, Alexander Graf wrote:
>> The bcm2835 frame buffer is in RAM, so we can easily map it as cached and
>> gain
>> all the glorious performance boost that brings with it.
>
> Tested-by: Stephen Warren
>
>> diff --git a
On 12.02.2016 14:24, Stefan Roese wrote:
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.
Signed-off-by: Stefan Roese
Cc: Luka Perkov
---
v2:
On 12.02.2016 13:52, Stefan Roese wrote:
These attribute defines may be used to map an area of memory for direct
access to the specific SPI devices. See SPI Direct Access Mode for
further information.
Signed-off-by: Stefan Roese
Cc: Luka Perkov
Applied to u-boot-marvell/master.
Thanks,
Stef
On 12.02.2016 13:52, Stefan Roese wrote:
The direct write config register is needed for SPI direct write mode
configuration.
Signed-off-by: Stefan Roese
Cc: Luka Perkov
Applied to u-boot-marvell/master.
Thanks,
Stefan
___
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U-Bo
On 12.02.2016 13:48, Stefan Roese wrote:
This patch adds support for programming of the StratixV FPGAs. Programming
is done in this case (board theadorable) via SPI. The board may provide
board specific code for bitstream programming.
This StratixV support will be used by the theadorable board.
On 12.02.2016 13:46, Stefan Roese wrote:
This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are
other non-DM drivers that might be used on these platforms. But this
patch creates a new DM driver. Which will be used by all Armada XP/38x
boards. Other MVEBU SoC (Kirkwood / Orion) ma
Hi Lokesh,
> dma_addr_t holds any valid DMA address. If the DMA API only uses
> 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus
> addresses, e.g., PCI BARs, may be wider than 32 bits, but drivers do
> memory-mapped I/O to ioremapped kernel virtual addresses, so they
> don't care about
On 02.02.2016 00:35, Chris Packham wrote:
Claim the MPP pins for the NAND flash controller only when it's actually
being used. This allows the pins to be shared with the SPI interface
which already supports an equivalent on-access MPP reconfiguration.
Reviewed-by: Mark Tomlinson
Signed-off-by:
On 28.10.2015 16:44, dirk.eib...@gdsys.cc wrote:
From: Dirk Eibach
Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.
Signed-off-by: Dirk Eibach
Applied to u-boot-marvell/master.
Thanks,
Stefan
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Hi Dennis,
On 27.01.2016 07:45, Stefan Roese wrote:
Hi Dennis,
On 15.01.2016 02:20, Dennis Gilmore wrote:
Switch all of the mvebu boards to support disto generic booting
This will enable Fedora, Debian and other distros to support
mvebu systems easier. Tested on SolidRun ClearFog
Sorry for t
On 17.01.2016 18:23, Peter Korsgaard wrote:
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition
layout (without any description why), but didn't change the offset/size to
load the kernel from or the root=/dev/mtdblockX in the bootargs.
The 3MB forseen for a kernel is fur
Hi,
I started to port my kernel to the secure world on a LS1021a board, so
I started to read the reference manual on the CSU component. In Table
9.8, we can see that
- Debug EPU is CSL47[24:16]
- DDDI is CSL48[24:16]
- Debug GDI is CSL48[8:0]
but in ns_access.h the order doesn't seem to fit. If I
York,
Thanks a lot for your answer and precisions.
On 23/03/16 16:56, york sun wrote:
> Valentin,
>
> Your understand is correct. Please see my answers below to your questions.
>
> On 03/23/2016 12:46 AM, Valentin Longchamp wrote:
>> Hello,
>>
>> We are currently designing a board based on the
Hello Tom,
On Wed, 23 Mar 2016 17:36:17 -0400, Tom Rini wrote:
> On Wed, Mar 23, 2016 at 06:08:45PM +0100, Albert ARIBAUD wrote:
> > Hello Tom,
> >
> > On Wed, 23 Mar 2016 09:22:38 -0400, Tom Rini wrote:
> > > On Wed, Mar 23, 2016 at 01:53:35PM +0100, Albert ARIBAUD wrote:
> > > > Hello Marek,
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