Hi Bin,
On 04.12.2015 07:17, Bin Meng wrote:
Hi,
On Fri, Dec 4, 2015 at 1:31 PM, Bin Meng wrote:
Hi Stefan,
On Thu, Dec 3, 2015 at 10:12 PM, Stefan Roese wrote:
Hi Bin,
On 03.12.2015 14:34, Bin Meng wrote:
Hi Stefan, Simon,
On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
On 29
On 3.12.2015 17:09, Jagan Teki wrote:
> On 3 December 2015 at 20:17, Michal Simek wrote:
>> CONFIG_API is causing compilation error when DM_ETH is enabled because
>> eth_get_dev() is not available.
>
> Then how come, freebsd elf generate w/o CONFIG_API?
missing DM support there.
Thanks,
Michal
Hi Simon,
On 03.12.2015 18:21, Simon Glass wrote:
> Hi Stefan,
>
> On 3 December 2015 at 04:31, Stefan Roese wrote:
>>
>> Hi Simon,
>>
>> On 02.12.2015 18:45, Simon Glass wrote:
>>> Hi Stefan,
>>>
>>> On 2 December 2015 at 10:43, Stefan Roese wrote:
Hi Simon,
( Last mail for toni
On Thu, Dec 3, 2015 at 10:48 PM, Michal Simek wrote:
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Mic
Hi,
On Fri, Dec 4, 2015 at 1:31 PM, Bin Meng wrote:
> Hi Stefan,
>
> On Thu, Dec 3, 2015 at 10:12 PM, Stefan Roese wrote:
>> Hi Bin,
>>
>>
>> On 03.12.2015 14:34, Bin Meng wrote:
>>>
>>> Hi Stefan, Simon,
>>>
>>> On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
On 29 September 2015
Hi Stefan,
On Thu, Dec 3, 2015 at 10:12 PM, Stefan Roese wrote:
> Hi Bin,
>
>
> On 03.12.2015 14:34, Bin Meng wrote:
>>
>> Hi Stefan, Simon,
>>
>> On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
>>>
>>> On 29 September 2015 at 23:00, Stefan Roese wrote:
The current "simple" addres
From: Shaohui Xie
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since its used
for MDIO, in FMAN v3, MDIO uses dedicated controller, so we can disable
the unused FM1-DTSEC1 MAC node to avoid it's being probed in kernel.
Signed-off-by: Shaohui Xie
---
drivers/net/fm/init.c | 4
1
Hi Oliver,
On Fri, Dec 4, 2015 at 3:49 AM, Olliver Schinagl wrote:
> From: Olliver Schinagl
>
> Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
> but forgot to enable the clocks for these 2 i2c busses.
>
> This patch enables the clocks for i2c bus 4 and 5 on sun7i.
>
> Sign
Hi Oliver,
On Fri, Dec 4, 2015 at 9:57 AM, Julian Calaby wrote:
> Hi Oliver,
>
> On Fri, Dec 4, 2015 at 3:49 AM, Olliver Schinagl wrote:
>> From: Olliver Schinagl
>>
>> Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
>> but forgot to enable the clocks for these 2 i2c busse
On 12/03/2015 05:55 PM, Jagan Teki wrote:
> On Thursday 03 December 2015 05:51 PM, Vignesh R wrote:
>>
>>
>> On 12/03/2015 05:25 PM, Jagan Teki wrote:
>>> On 23 November 2015 at 17:43, Vignesh R wrote:
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped
On 4 December 2015 at 06:41, Peng Fan wrote:
> Hi Jagan,
> On Thu, Dec 03, 2015 at 05:21:09PM +0530, Jagan Teki wrote:
>>On 30 November 2015 at 15:31, Stefano Babic wrote:
>>> On 30/11/2015 10:45, Peng Fan wrote:
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2.
Hi York,
Please see my explanation inline.
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Friday, December 04, 2015 12:27 AM
> To: Tang Yuantian-B29983
> Cc: u-boot@lists.denx.de; si...@writeme.com
> Subject: Re: [PATCH v5] arm: Add sata support on Layerscap
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/bcm_udc_otg_phy.c | 4 +--
drivers/usb/gadget/s3c_udc_otg.c | 46 +++
Rename the header file, so it's obvious which driver it's part of.
No functional change.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 2 +-
drivers/usb/gadget/s3c_udc_otg_phy.c | 2 +-
drivers/usb/gadget/{regs-otg.h => s3c_udc_otg_regs.h
Just staticize the functions, they are not used outside of the file.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
b/drivers/usb/gadget/s3c_udc
The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg_priv.h | 6 ++
include/usb/s3c_udc.h | 2 +-
2 files changed, 3 insertions(+), 5 deletions(-)
dif
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 6 +++---
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 22 +++---
2 files changed, 1
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 36 +++
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 10 -
Just change the driver name.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index a960eff..9cb6849 100644
--- a/drivers/usb/gadget/s3c_ud
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.
The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`
Si
The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/dwc2_udc_otg.c | 2 +-
drivers/usb/gadget/dwc2_udc_otg_phy.c | 2 +-
drivers/usb/gadget/dwc2_udc_otg_priv.h | 2 +-
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.
The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`
Signed-off-by: Marek Vasut
---
board/
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 18
drivers/usb/gadget/s3c_udc_otg_priv.h | 2 +-
drivers/usb/gadget/s3c_udc_otg_xfer
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 18
dri
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.
The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`
Sig
Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/bcm_udc_otg_phy.c
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg_phy.c | 8
drivers/usb/gadget/s3c_udc_otg_regs.h | 2 +-
2
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:
git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
while read line ; do
sed -i "s/USB_G
The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/Makefile | 4 ++--
drivers/usb/gadget/{s3c_ud
The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/bcm_udc_otg_phy.c | 2 +-
drivers/usb/gadget/{s3c_udc_otg_priv
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/dwc2_udc_otg.c | 14 +++---
drivers/usb/gadget/dwc2_udc_otg_priv.h | 6 +++---
drivers/usb/ga
This function is local to s3c_udc_otg_xfer_dma.c , staticize it.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg_priv.h | 2 --
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/s3c_udc_otg_priv.h
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/gadget/
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 38
drivers/usb/gadget/s3c_udc_otg_priv.h | 6 ++--
drivers/usb/gadget/s3c_udc_otg
The driver is for the dwc2 otg block , so rename it accordingly finally.
Marek Vasut (24):
usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h
usb: s3c-otg: Rename struct s3c_udc to dwc2_udc
usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg
usb: s3c-otg: Split private bits fr
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg_regs.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/gadget/s3c_udc_otg_regs.
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.
Signed-off-by: Marek Vasut
---
drivers/usb/gadget/s3c_udc_otg.c | 4 ++--
drivers/usb/gadget/s3c_udc_otg_regs.h | 2 +-
2 file
> On 12/03/2015 01:49 AM, Wang Huan-B18965 wrote:
>
>
>
> >>
> >> The actual command which results in a watchdog reset is 'sf read
> >> 0x8104 0x20 0x40'. Please note that this uses an external
> >> watchdog which is enabled by default and resets after ~1.5s. The
> >> command itself
> On Thursday 03 December 2015 09:49:40, Huan Wang wrote:
> > [Alison Wang] I could not reproduce the issue. Maybe I don't have the
> > external watchdog which will reset after ~1.5s as Alexander mentioned.
>
> Could you try to set the internal watchdog to 1s timeout? This should be
> more or less
Hi Jagan,
On Thu, Dec 03, 2015 at 05:21:09PM +0530, Jagan Teki wrote:
>On 30 November 2015 at 15:31, Stefano Babic wrote:
>> On 30/11/2015 10:45, Peng Fan wrote:
>>> Support qspi flashes for mx7dsabresd
>>> 1. introduce pin mux settings
>>> 2. enable qspi clock
>>> 3. introduce related macro defin
On Thursday, December 03, 2015 at 09:07:18 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
> the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so
> that the reading the bsel can generi
On Thursday, December 03, 2015 at 11:05:59 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with
> __CONFIG_SOCFPGA_OMMON_H__ as the file is now called socfpga_common.h
COMMON, not OMMON ... please be more careful next time.
> Signed
hey,
i've been using the master branch of u-boot on the odroid xu4 now! i had
to write this patch in order to make it work with NIXOS.
would be great if you could apply it. please review it, not 100% sure if
it is correct.
best wishes,
joachim
MAX_TFTP_PATH_LEN-increase.patch
A patch to mak
On Thursday, December 03, 2015 at 11:08:59 PM, Dinh Nguyen wrote:
> On 12/02/2015 08:42 PM, Marek Vasut wrote:
> > On Wednesday, December 02, 2015 at 08:31:26 PM,
> > dingu...@opensource.altera.com
> >
> > wrote:
> >> From: Dinh Nguyen
> >>
> >> Add system manager defines for Arria10.
> >>
> >>
On 12/03/2015 02:43 PM, Simon Glass wrote:
Hi Stephen,
On 3 December 2015 at 14:33, Stephen Warren wrote:
On 11/22/2015 08:53 AM, Tom Rini wrote:
On Thu, Nov 19, 2015 at 09:48:11PM +0800, Thomas Chou wrote:
Unify serial_tegra, and use the generic binding.
Signed-off-by: Thomas Chou
Revie
Seems 92a655c3 broke creating multi and script type images.
Since the file1:file2:file3 string does not get split up,
it fails on trying to open an non-existing file.
mkimage -A arm -O linux -T multi -C none -d zImage:splash.bmp:device.dtb uimage
tools/mkimage: Can't open zImage:splash.bmp:device
The MC version numbers provide no meaningful information
about binary interface compatibility, so remove the
check which refuses to start the MC unless a specific
version is found.
Version checking is supposed to be done at the individual
object level, and individual drivers are responsible
for th
On 12/02/2015 08:42 PM, Marek Vasut wrote:
> On Wednesday, December 02, 2015 at 08:31:26 PM,
> dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Add system manager defines for Arria10.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> v4: none
>> v3: combine system_manager_a10.h into
From: Dinh Nguyen
Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with
__CONFIG_SOCFPGA_OMMON_H__ as the file is now called socfpga_common.h
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/soc
Hi,
On 3 December 2015 at 14:55, Nye Liu wrote:
>
> On 11/19/2015 6:15 AM, Simon Glass wrote:
>> Hi,
>>
>> On 18 November 2015 at 17:37, Nye Liu wrote:
>>> ---
>>> tools/mkimage.c | 32 +++-
>>> 1 file changed, 19 insertions(+), 13 deletions(-)
>>>
>>
>> Can you plea
Hi,
On 3 December 2015 at 14:35, Stephen Warren wrote:
> On 11/19/2015 08:26 PM, Simon Glass wrote:
>>
>> Move this option to Kconfig and fix up all users.
>
>
> The version of this that got committed (as fde7e18938d8) contains merge
> markers in a four files.
Ugh. I had that problem locally in
Hi Stephen,
On 3 December 2015 at 14:33, Stephen Warren wrote:
> On 11/22/2015 08:53 AM, Tom Rini wrote:
>>
>> On Thu, Nov 19, 2015 at 09:48:11PM +0800, Thomas Chou wrote:
>>
>>> Unify serial_tegra, and use the generic binding.
>>>
>>> Signed-off-by: Thomas Chou
>>> Reviewed-by: Tom Rini
>>> Ac
On 11/19/2015 08:26 PM, Simon Glass wrote:
Move this option to Kconfig and fix up all users.
The version of this that got committed (as fde7e18938d8) contains merge
markers in a four files.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.d
On 11/22/2015 08:53 AM, Tom Rini wrote:
On Thu, Nov 19, 2015 at 09:48:11PM +0800, Thomas Chou wrote:
Unify serial_tegra, and use the generic binding.
Signed-off-by: Thomas Chou
Reviewed-by: Tom Rini
Acked-by: Simon Glass
Applied to u-boot/master, thanks!
FYI, this patch causes at least
On Thursday, December 03, 2015 at 07:35:54 PM, Pavel Machek wrote:
> > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > + puts("CPU : Altera SOCFPGA Arria 10 Platform\n");
> >
> > No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> > platform", CPU is still Altera SoCFPGA
From: Dinh Nguyen
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/ma
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v5: rename the mod_reest on A10 to match those in gen5
v4: rename mod_reset names to be used by both gen5 and a10
v3: remove duplicate reset function
use CONFIG_SOCFPGA
On 12/02/2015 08:47 PM, Marek Vasut wrote:
> On Wednesday, December 02, 2015 at 08:31:28 PM,
> dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Add arch_early_init_r function. The Arria10 has a firewall protection
>> around the SDRAM and OCRAM. These firewalls are to be disable
Hi Tom,
2015-12-03 13:19 GMT+01:00 Tom Rini :
> On Thu, Dec 03, 2015 at 09:40:46AM +0100, Dirk Eibach wrote:
>> Hi Tom,
>>
>> 2015-12-01 21:50 GMT+01:00 Tom Rini :
>> > In order to fit into image constraints again, remove this feature.
>> >
>> > Signed-off-by: Tom Rini
>> > ---
>> > configs/ioco
Hi Joe,
On 3 December 2015 at 12:00, Joe Hershberger wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 12:57 PM, Simon Glass wrote:
>>
>> On 3 December 2015 at 07:48, Michal Simek wrote:
>> >
>> > - Enable DM_ETH by default for Zynq and ZynqMP
>> > - Remove board_eth_init code
>> > - Change miiphy_
Hi Simon,
On Thu, Dec 3, 2015 at 12:57 PM, Simon Glass wrote:
>
> On 3 December 2015 at 07:48, Michal Simek wrote:
> >
> > - Enable DM_ETH by default for Zynq and ZynqMP
> > - Remove board_eth_init code
> > - Change miiphy_read function to return value instead of error code
> > based on DM req
On 3 December 2015 at 10:12, Jagan Teki wrote:
> SPI_3WIRE is spi mode not spi flags, so this patch fixed
> the spi-3wire checking throgh mode instead of flags.
>
> Cc: Mugunthan V N
> Cc: Simon Glass
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/ti_qspi.c | 2 +-
> 1 file changed, 1 inserti
On 3 December 2015 at 07:48, Michal Simek wrote:
>
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Micha
On 3 December 2015 at 10:12, Jagan Teki wrote:
> spi-3wire is used when SI/SO signals shared so get
> the same from dts node and assign to mode on slave
> plat->mode.
>
> Cc: Simon Glass
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/spi-uclass.c | 2 ++
> 1 file changed, 2 insertions(+)
Acke
Hi,
On 3 December 2015 at 06:27, Bin Meng wrote:
> Hi Jagan,
>
> On Thu, Dec 3, 2015 at 6:24 PM, Jagan Teki wrote:
>> Hi Bin,
>>
>> On 3 December 2015 at 10:14, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
+Jagan
Hi Bin,
On 1
Hi Bin,
On 2 December 2015 at 22:22, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:59, Bin Meng wrote:
>>> Since VPD/UPD may not exist on every FSP, move the codes that
>>> verifies VPD/UPD to chipset-specific update
Hi Bin,
On 2 December 2015 at 22:18, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:59, Bin Meng wrote:
>>> FSP has several config data like UPD, HDA verb table which can be
>>> overridden or provided by bootloader. C
Hi Michal,
On 2 December 2015 at 22:00, Bin Meng wrote:
> Hi Michal,
>
> On Wed, Dec 2, 2015 at 9:51 PM, Michal Simek wrote:
>> On 2.12.2015 14:16, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Wed, Dec 2, 2015 at 7:36 PM, Michal Simek
>>> wrote:
>>
>> ...
>>
+
+ offset = fdtdec_lo
Hi Bin,
On 2 December 2015 at 21:57, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Nov 26, 2015 at 12:52 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 19 November 2015 at 20:38, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Fri, Nov 20, 2015 at 11:09 AM, Simon Glass wrote:
Hi,
I'm wondering w
Hi Bin,
On 2 December 2015 at 22:11, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 2 December 2015 at 01:58, Bin Meng wrote:
>>> There is no need to pass shared_data to fsp_continue() so we can
>>> remove unnecessary codes that simplifies
On Wed 2015-12-02 13:31:27, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Add the defines for the reset manager and some basic reset functionality.
>
> Signed-off-by: Dinh Nguyen
> ---
> v4: rename mod_reset names to be used by both gen5 and a10
> v3: remove duplicate reset func
On Tue 2015-12-01 17:33:02, Dinh Nguyen wrote:
> On 12/01/2015 05:30 PM, Marek Vasut wrote:
> > On Wednesday, December 02, 2015 at 12:20:47 AM,
> > dingu...@opensource.altera.com
> > wrote:
> >> From: Dinh Nguyen
> >>
> >> Not sure what made this macro questionable, but edit the macro to be
> >>
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > + puts("CPU : Altera SOCFPGA Arria 10 Platform\n");
>
> No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> platform",
> CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?
>
Well. .. cpu is "gener
On Tue 2015-12-01 19:51:39, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 05:48:32 PM, dingu...@opensource.altera.com
> wrote:
> > From: Dinh Nguyen
> >
> > Add the defines for the reset manager and some basic reset functionality.
> >
> > Signed-off-by: Dinh Nguyen
> > ---
> > v2: inte
On Tue 2015-12-01 10:48:31, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Add system manager defines for Arria10.
>
> Signed-off-by: Dinh Nguyen
With whitespace cleaned up:
Acked-by: Pavel Machek
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http:/
Hi!
> > > OK, this is bad. Originally, if we didn't specify these in the DT, we
> > > would
> > > use the default values of 0x3 and 0x0 , but now we do the
> > > calibration. I wonder,
> > > do we care about DT ABI compatibility on the U-Boot level or not ?
> >
> > If the compatibility failed, it
Hi,
On 03-12-15 17:09, Jagan Teki wrote:
On 3 December 2015 at 20:17, Michal Simek wrote:
CONFIG_API is causing compilation error when DM_ETH is enabled because
eth_get_dev() is not available.
Then how come, freebsd elf generate w/o CONFIG_API?
Signed-off-by: Michal Simek
---
Changes in v
SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.
Cc: Mugunthan V N
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
drivers/spi/ti_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/ti_qspi.c b/driver
Hi Stefan,
On 3 December 2015 at 04:31, Stefan Roese wrote:
>
> Hi Simon,
>
> On 02.12.2015 18:45, Simon Glass wrote:
> > Hi Stefan,
> >
> > On 2 December 2015 at 10:43, Stefan Roese wrote:
> >> Hi Simon,
> >>
> >> ( Last mail for tonight - a glass of quite nice red wine is
> >> waiting for me .
spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
drivers/spi/spi-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
inde
On 12/02/2015 04:15 PM, Stefan Brüns wrote:
pxe get derives the pxelinux config file name from the bootfile name,
but the bootfile itself is never used and might not even exist.
Disable bootfile autoload to avoid the delay.
I wasn't CC'd on this and only accidentally noticed it, since it just
From: Olliver Schinagl
Add some spaces around operators.
Signed-off-by: Olliver Schinagl
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index e
From: Olliver Schinagl
Paul enabled all I2C ports for sunxi but forgot the clock on twi 4 and 5 for
sun7i.
And a small non code changing whitespace fix
Tested on Olimex Lime2
Olliver Schinagl (2):
sunxi: twi: enable clocks on sun7i
sun4i: clock: cleanup some whitespace errors
arch/arm/c
From: Olliver Schinagl
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to enable the clocks for these 2 i2c busses.
This patch enables the clocks for i2c bus 4 and 5 on sun7i.
Signed-off-by: Olliver Schinagl
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 4
On 12/03/2015 07:12 AM, Stefan Roese wrote:
Hi Bin,
On 03.12.2015 14:34, Bin Meng wrote:
Hi Stefan, Simon,
On Mon, Oct 19, 2015 at 7:16 AM, Simon Glass wrote:
On 29 September 2015 at 23:00, Stefan Roese wrote:
The current "simple" address translation simple_bus_translate() is not
working o
Hi Simon,
On 26 November 2015 at 23:20, Simon Glass wrote:
> Hi Jagan,
>
> On 26 November 2015 at 04:03, Jagan Teki wrote:
>> flash operations are defined as static and reuse them
>> with function-pointers so call them with generic
>> function pounters instead of calling like normal functions.
>
On 12/01/2015 07:27 PM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Freescale ARM-based Layerscape contains a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> ls
On 3 December 2015 at 20:17, Michal Simek wrote:
> Check return value.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
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On 3 December 2015 at 20:17, Michal Simek wrote:
> Sync it with write function.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
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On 3 December 2015 at 20:17, Michal Simek wrote:
> Add return value for phy detection algorithm to stop init function when
> phy is not found.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
U-Boot mailing list
U-
On 3 December 2015 at 20:17, Michal Simek wrote:
> This function was used for OF init before DM.
> Remove this function as the part of move to DM.
>
> Signed-off-by: Michal Simek
> Reviewed-by: Simon Glass
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
__
On Thursday, December 03, 2015 at 05:11:23 PM, Chin Liang See wrote:
[...]
> > I have another board where I cannot use UBI on QSPI NOR and reverting
> > this
> > patch magically fixes things.
>
> I was testing this too as enabling the UBIFS on NOR and here are my
> output. Wonder how to simulate
On 3 December 2015 at 20:18, Michal Simek wrote:
> Do not set interface via configs. Read information from DT.
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
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On 3 December 2015 at 20:18, Michal Simek wrote:
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
>
> Changes in v3: None
> Changes in v2: None
>
> configs/xilinx_zynqmp_ep_defconfig | 1 +
> configs/zynq_microzed_defconfig| 1 +
> configs/zynq_picozed_defconfig | 1 +
> co
On 3 December 2015 at 20:18, Michal Simek wrote:
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Michal
On Thu, 2015-12-03 at 01:10 +0100, Marek Vasut wrote:
> On Thursday, November 12, 2015 at 03:33:42 AM, Chin Liang See wrote:
> > On Thu, 2015-11-12 at 01:53 +0100, Marek Vasut wrote:
> > > On Thursday, November 12, 2015 at 01:49:09 AM, Chin Liang See
> > > wrote:
> > > > Hi Marek,
> > > >
> > > >
On 3 December 2015 at 20:17, Michal Simek wrote:
> Move PHYLIB from board config to defconfig
>
> Signed-off-by: Michal Simek
> ---
Reviewed-by: Jagan Teki
thanks!
--
Jagan.
___
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On 3 December 2015 at 20:17, Michal Simek wrote:
> CONFIG_API is causing compilation error when DM_ETH is enabled because
> eth_get_dev() is not available.
Then how come, freebsd elf generate w/o CONFIG_API?
>
> Signed-off-by: Michal Simek
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>
On 19 November 2015 at 12:35, Mugunthan V N wrote:
> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
>
> Signed-off-by: Mugunthan V N
> Reviewed-by: S
On 12/03/2015 01:49 AM, Wang Huan-B18965 wrote:
>>
>> The actual command which results in a watchdog reset is 'sf read
>> 0x8104 0x20 0x40'. Please note that this uses an external
>> watchdog which is enabled by default and resets after ~1.5s. The command
>> itself takes about 2s (
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