The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
drivers/usb/gadget/s3c_udc_otg_phy.c | 8 ++++----
drivers/usb/gadget/s3c_udc_otg_regs.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c
b/drivers/usb/gadget/s3c_udc_otg_phy.c
index 169f8e4..a761b43 100644
--- a/drivers/usb/gadget/s3c_udc_otg_phy.c
+++ b/drivers/usb/gadget/s3c_udc_otg_phy.c
@@ -41,8 +41,8 @@
void otg_phy_init(struct dwc2_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
- struct s3c_usbotg_phy *phy =
- (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+ struct dwc2_usbotg_phy *phy =
+ (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
dev->pdata->phy_control(1);
@@ -79,8 +79,8 @@ void otg_phy_init(struct dwc2_udc *dev)
void otg_phy_off(struct dwc2_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
- struct s3c_usbotg_phy *phy =
- (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+ struct dwc2_usbotg_phy *phy =
+ (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
/* reset controller just in case */
writel(PHY_SW_RST0, &phy->rstcon);
diff --git a/drivers/usb/gadget/s3c_udc_otg_regs.h
b/drivers/usb/gadget/s3c_udc_otg_regs.h
index c8da803..e5115dd 100644
--- a/drivers/usb/gadget/s3c_udc_otg_regs.h
+++ b/drivers/usb/gadget/s3c_udc_otg_regs.h
@@ -12,7 +12,7 @@
#define __ASM_ARCH_REGS_USB_OTG_HS_H
/* USB2.0 OTG Controller register */
-struct s3c_usbotg_phy {
+struct dwc2_usbotg_phy {
u32 phypwr;
u32 phyclk;
u32 rstcon;
--
2.1.4
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