Hi Simon,
On Mon, 15 Dec 2014 07:19:39 -0700
Simon Glass wrote:
> diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
> index 7b1f368..ed790cc 100644
> --- a/include/configs/canyonlands.h
> +++ b/include/configs/canyonlands.h
> @@ -11,6 +11,8 @@
> #ifndef __CONFIG_H
> #
The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.
There is already a driver for the mv88e61xx in U-Boot, and this patch
updates it to also work with the mv8
At present U-Boot sort-of supports the standard way of reading GPIOs from
device tree nodes, but the support is incomplete, a bit clunky and only
works for GPIO bindings where #gpio-cells is 2.
Also, this support can now be built into the uclass, rather than parked in
a separate file.
Add support
Add support for a sun4i board built by Linksprite. This addition covers
both v1 and v2 versions. As the board has been working with 408MHz memory
setting in the u-boot-sunxi branch, and has been proven to be running stable
during my tests as well, a respective new DRAM config file is added as well.
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng
---
include/configs/chromebook_link.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index e0bf309..7e
We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3,
there are 4 i2c interface, but not 3. So the size of i2c_data array should
be calculated using "ARRAY_SIZE(i2c_bases)".
To avoid compile error, move i2c_bases before sram_data structure which
contains i2c_data array.
Signed-
Hi Simon,
On Sat, 27 Dec 2014 10:32:38 -0700
Simon Glass wrote:
> >
> > [2] It is difficult to describe alias register name for the same address.
> >
> > For example,
> >
> > #define I2C_DTTX0x04/* send FIFO */
> > #define I2C_DTRX0x04/* receive FIFO */
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass
Signed-off-by: Bin Meng
---
arch/x86/cpu/queensbay/fsp_support.c | 10 +++---
arch/x8
The pattern "N:uniphier" can cover
- drivers/serial/serial_uniphier.c
- drivers/i2c/i2c-uniphier.c
- drivers/i2c/i2c-uniphier-f.c
Signed-off-by: Masahiro Yamada
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6041936.
The low-level debugging functions are useful to debug the early boot
stage where the full UART driver is not available.
UniPhier SoCs need to initialize the UART port 0 to use this feature.
The initialization routine is called at the very entry of the
lowlevel_init().
Signed-off-by: Masahiro Yama
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
board/coreboot/coreboot/coreboot.c | 2 ++
1 file changed, 2 ins
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to configure pci memory regions
arch/x86/cpu/coreboot/pci.c | 30 +++
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3:
- Fix several typos in README.x86
Changes in v2:
- New patch to update REAME.x8
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Chang
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition o
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to remove include/configs/coreboot.h
board/co
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-of
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is
not selected
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, s
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to move CONFIG_X86_RESET_VECTOR and CONFI
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 7 +++
arch/arm/cpu/armv7/uniph
The max size of available memories on slot0 and slot1 is 32MB because
- EA[25] signal is not output on the save-pin mode which is
used PH1-LD4 or later SoCs.
- EA[25] signal is not connected by the limitation (or bug?) of
the PLD logic of DCC support card.
Signed-off-by: Masahiro Yamada
-
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/ph1_ld4_defconfig | 2 ++
configs/ph1_pro4_defconfig | 2 ++
configs/ph1_sld8_defconfig | 2 ++
3 files changed, 6 insertions(+)
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defc
Signed-off-by: Masahiro Yamada
---
To apply this commit, the following must be applied in advance:
http://patchwork.ozlabs.org/patch/422543/
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/uniphier.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/co
This commit adds on-chip I2C driver used on some old Panasonic
UniPhier SoCs.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
Acked-by: Heiko Schocher
---
Changes in v4:
- Use a structure instead of macros for register access
Changes in v3: None
Changes in v2:
- Fix a typo. s/fre
Masahiro Yamada (5):
i2c: add CONFIG_DM_I2C to Kconfig
i2c: UniPhier: add driver for UniPhier i2c controller
i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controller
ARM: UniPhier: enable I2C for UniPhier SoCs
ARM: UniPhier: enable CONFIG_I2C_EEPROM
configs/ph1_ld4_defconfig
This commit adds on-chip I2C driver used on newer SoCs of Panasonic
UniPhier platform.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
Acked-by: Heiko Schocher
---
Changes in v4:
- Use a structure instead of macros for register access
Changes in v3:
- Fix a bug in that device busy
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
Acked-by: Heiko Schocher
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/i2c/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index e69de29..96715d0 10064
Hi Simon,
On Tue, Jan 6, 2015 at 12:20 PM, Bin Meng wrote:
> In theory U-Boot built for coreboot is supposed to run as a payload
> to be loaded by coreboot on every board that coreboot supports.
> The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
> which are hardcoded in board
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, s
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Hi,
On Tue, Jan 6, 2015 at 12:20 PM, Bin Meng wrote:
> Update README.x86 to include new build instructions for U-Boot as
> the coreboot payload and testing considerations with coreboot.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Fix
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition o
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
board/coreboot/coreboot/coreboot.c | 2 ++
1 file changed, 2 insertions(+)
diff --g
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- New patch to configure pci memory regions
arch/x86/cpu/coreboot/pci.c | 30 --
1 file chan
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Fix several typos in README.x86
- New patch to update REAME.x86 for coreboot s
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is
not selected
arch/x86/Kconfig | 1
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Chang
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-of
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- New patch to remove include/configs/coreboot.h
board/coreboot/coreboot/MAIN
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- New patch to move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want
This deals with the polarity bit and selecting the correct bank device
given a GPIO number.
Signed-off-by: Simon Glass
---
drivers/gpio/tegra_gpio.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 88f7ef5..43928
These functions serve no useful purpose, and conflict with the generic API.
Drop them.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-zynq/gpio.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h
b/arch/arm/include/asm/arch-zynq
So far driver model's GPIO uclass just implements the existing GPIO API.
This has some limitations:
- it requires manual device tree munging to support GPIOs in device tree
(fdtdec_get_gpio() and friends)
- it does not understand polarity
- it is somewhat slower since we must scan for the GPIO
U-Boot now supports using GPIOs using bank phandles instead of global
numbers. Update the exynos device tree files to use this.
Signed-off-by: Simon Glass
---
arch/arm/dts/exynos4.dtsi | 7 ---
arch/arm/dts/exynos4210-origen.dts | 2 +-
arch/arm/dts/exynos4210-tra
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-pantheon/gpio.h | 0
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 7 +++---
drivers/mmc/s5p_sdhci.c | 20 +++-
drivers/mmc/tegra_m
Now that we support device tree GPIO bindings directly in the driver model
GPIO uclass we can remove these functions.
Signed-off-by: Simon Glass
---
include/fdtdec.h | 77 -
lib/fdtdec.c | 95 ---
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
drivers/spi/soft_spi.c | 62 +++---
1 file changed, 28 insertions(+), 34 deletions(-)
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
i
Add a deprecation notice to each function so that it is more obvious that we
are moving GPIOs to driver model.
Signed-off-by: Simon Glass
---
include/asm-generic/gpio.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gp
For GPIOs and other functions we want to look up a phandle and then decode
a list of arguments for that phandle. Each phandle can have a different
number of arguments, specified by a property in the target node. This is
the "#gpio-cells" property for GPIOs.
Add a function to provide this feature,
Only the GPIO driver knows about the full GPIO device tree binding used by
a device. Add a method to allow the driver to provide this information to the
uclass, including the GPIO offset within the device and flags such as the
polarity.
Signed-off-by: Simon Glass
---
drivers/gpio/gpio-uclass.c
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
drivers/mtd/nand/tegra_nand.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 163cf29..b660f3b 1
This deals with the polarity bit. It also changes the GPIO devices so that
the correct device tree node is linked to each one. This allows us to use
the new uclass phandle functionality to implement a proper GPIO binding.
Signed-off-by: Simon Glass
---
drivers/gpio/s5p_gpio.c | 13 -
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec.c | 24 ++--
include/cros_ec.h | 3 ++-
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
drivers/usb/host/ehci-exynos.c | 10 +-
drivers/usb/host/ehci-tegra.c | 38 ++
drivers/usb/host/xhci-exynos5.c | 10 +-
3 files changed, 2
This new method is much easier and matches the kernel.
Signed-off-by: Simon Glass
---
arch/arm/dts/tegra114-dalmore.dts | 5 ++---
arch/arm/dts/tegra124-jetson-tk1.dts | 9 +
arch/arm/dts/tegra124-venice2.dts | 9 +
arch/arm/dts/tegra20-colibri_t20_iris.d
At present the tegra GPIO driver does not fully support the existing device
tree binding, but add the binding file to cover the existing partial support.
Signed-off-by: Simon Glass
---
.../gpio/nvidia,tegra20-gpio.txt | 40 ++
1 file changed, 40 insertions(
Add the binding file that we are about to support.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/gpio/gpio.txt | 211 +
1 file changed, 211 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/gpio.txt
diff --git a/doc/device-tree-bindings/g
Add a new 'demo light' command which uses GPIOs to control imaginary lights.
Each light is assigned a bit number in the overall value. This provides an
example driver for using the new GPIO API.
Signed-off-by: Simon Glass
---
arch/sandbox/dts/sandbox.dts | 11 ++-
common/cmd_demo.c
At present the exynos GPIO driver does not fully support the existing device
tree binding, but add the binding file to cover the existing partial support.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/gpio/gpio-samsung.txt | 41 ++
1 file changed, 41 insertions
At present U-Boot sort-of supports the standard way of reading GPIOs from
device tree nodes, but the support is incomplete, a bit clunky and only
works for GPIO bindings where #gpio-cells is 2.
Add new functions to request GPIOs, taking full account of the device
tree binding. These permit request
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-tegra20/display.h | 9 ++---
drivers/video/tegra.c | 54 +++--
2 files changed, 25 insertions(+), 38 deletions(-)
diff
Hi Simon,
On Tue, Jan 6, 2015 at 10:38 AM, Simon Glass wrote:
> Hi Bin,
>
> On 5 January 2015 at 19:14, Bin Meng wrote:
>> Hi Simon,
>>
>> On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>> On 5 January 2015 at 08:28, Bin Meng wrote:
>>>
>>> nit: coreboot-specific defines
>
Hi Bin,
On 5 January 2015 at 06:54, Bin Meng wrote:
> Hi Simon,
>
> On Mon, Jan 5, 2015 at 9:49 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 4 January 2015 at 00:49, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Tue, Dec 30, 2014 at 9:12 AM, Simon Glass wrote:
The memory reference code takes a v
Hi Masahiro,
On 5 January 2015 at 07:56, Masahiro YAMADA wrote:
> Hi Simon,
>
>
> 2014-12-22 3:53 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> On 20 December 2014 at 00:25, Masahiro YAMADA
>> wrote:
>>> Hi Simon,
>>>
>>>
>>> 2014-12-20 6:34 GMT+09:00 Simon Glass :
Hi Masahiro,
O
Hi Masahiro,
On 5 January 2015 at 07:32, Masahiro YAMADA wrote:
> Hi Simon,
>
>
> 2015-01-05 11:11 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> I notice that when compiling I get the full paths to the source when I
>> use __FILE__:
>>
>> /home/sjg/c/src/third_party/u-boot/files/cros/lib/readwrit
Hi Bin,
On 5 January 2015 at 19:31, Bin Meng wrote:
> Hi Simon,
>
> On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 5 January 2015 at 08:28, Bin Meng wrote:
>>> Update README.x86 to include new build instructions for U-Boot as
>>> the coreboot payload and testing consider
Hi Bin,
On 5 January 2015 at 19:14, Bin Meng wrote:
> Hi Simon,
>
> On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 5 January 2015 at 08:28, Bin Meng wrote:
>>
>> nit: coreboot-specific defines
>
> OK.
>
>>> There are many places in the U-Boot source tree which refer to
>
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
> Hi Bin,
>
> On 5 January 2015 at 08:28, Bin Meng wrote:
>> Update README.x86 to include new build instructions for U-Boot as
>> the coreboot payload and testing considerations with coreboot.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
> Hi Bin,
>
> On 5 January 2015 at 08:28, Bin Meng wrote:
>> Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
>> which is currently the only real board officially supported to run
>> U-Boot loaded by coreboot.
>>
>> No
Hi Tom,
Please see my patch carefully.
http://patchwork.ozlabs.org/patch/415041/
Your commit (1bf0979f5ff4c297) added the expert menu at the root menu.
Mine moves it under the "General setup" menu like Linux.
On Mon, 5 Jan 2015 12:41:56 -0500
Tom Rini wrote:
> On Tue, Jan 06, 2015 at 12
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass wrote:
> Hi Bin,
>
> On 5 January 2015 at 08:28, Bin Meng wrote:
>
> nit: coreboot-specific defines
OK.
>> There are many places in the U-Boot source tree which refer to
>> CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng wrote:
> Update README.x86 to include new build instructions for U-Boot as
> the coreboot payload and testing considerations with coreboot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to update REAME.x86 for coreboot support
>
On 5 January 2015 at 08:28, Bin Meng wrote:
> Since we already swtiched to use the new mechanism for building
> U-Boot for coreboot, coreboot.h is no longer needed so remove it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to remove include/configs/coreboot.h
>
> board/co
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng wrote:
> Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
> which is currently the only real board officially supported to run
> U-Boot loaded by coreboot.
>
> Note the symbolic link file chromebook_link.dts is deleted and
> link.dts i
On 5 January 2015 at 08:28, Bin Meng wrote:
> cros_ec_board_init() should be called only when CONFIG_CROS_EC is
> enabled.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - Leave CROS_EC defines unchanged in coreboot.h
>
> board/coreboot/coreboot/coreboot.c | 2 ++
> 1 file changed, 2 i
On 5 January 2015 at 08:28, Bin Meng wrote:
> Configure coreboot pci memory regions so that pci device drivers
> could work correctly.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to configure pci memory regions
>
> arch/x86/cpu/coreboot/pci.c | 30 +++
On 5 January 2015 at 08:28, Bin Meng wrote:
> Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
> we don't need them in the board configuration file thus the same
> board configuratoin file can be used to build both coreboot version
> and bare version.
>
> Signed-off-by: Bin Meng
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng wrote:
nit: coreboot-specific defines
> There are many places in the U-Boot source tree which refer to
> CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
> that is currently defined in coreboot.h.
>
> Move them to arch/x86/cpu/core
On 5 January 2015 at 08:28, Bin Meng wrote:
> In theory U-Boot built for coreboot is supposed to run as a payload
> to be loaded by coreboot on every board that coreboot supports.
> The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
> which are hardcoded in board defconfig and K
On 5 January 2015 at 08:28, Bin Meng wrote:
> By default U-Boot automatically calibrates TSC running frequency via
> MSR and PIT. The calibration may not work on every x86 processor, so
> a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
> allow bypassing the calibration and assi
On 5 January 2015 at 08:28, Bin Meng wrote:
> Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
> options so that we can remove them from board configuration file.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to move CONFIG_X86_RESET_VECTOR and CONFIG_S
On 5 January 2015 at 08:27, Bin Meng wrote:
> If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
> of base_time in coreboot's timestamp table as our timer base,
> otherwise TSC counter value will be used.
>
> Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
> the va
On 5 January 2015 at 08:28, Bin Meng wrote:
> When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
> size is meaningless, hence hide it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is
> not selected
>
>
Hi Tom,
This didn't go through last time, it is on branch 'misc'.
The following changes since commit d622ac39274a949b6445f1bfd92dc1644014388b:
powerpc: mpc824x: remove MPC824X cpu support (2015-01-05 12:08:55 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git
Hi Tom,
On 29 December 2014 at 19:26, Tom Rini wrote:
> On Mon, Dec 29, 2014 at 03:07:41PM -0700, Simon Glass wrote:
>
>> Hi Tom,
>>
>> Here are a few misc fixes and updates. Note that the branch is 'misc'
>> (there is also a 'master' branch pull out there).
>>
>>
>> The following changes since c
On Mon, Jan 5, 2015 at 8:41 PM, Fabio Estevam wrote:
> +ENTRY(relocate_vectors)
> +
> + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
> + ldr r1, =32 /* size of vector table */
> + add r0, r0, r1 /* skip to indirect table */
> +
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
register write fails so the latest valid value should be fifo - 1.
2
From: Fabio Estevam
Since commit ("arm: relocate the exception vectors") mx25pdk hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
We need to add a specific relocate_vectors macro, just like it was done for
mx27 SoC in
From: Fabio Estevam
Since commit ("arm: relocate the exception vectors") mx25pdk hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
We need to add a specific relocate_vectors macro, just like it was done for
mx27 SoC in
Hi Bill,
On Mon, Jan 5, 2015 at 8:25 PM, Bill Pringlemeir wrote:
> $ git show 3ff46cc42b9d73d01c86df9044257
>
> /*
> * Default/weak exception vectors relocation routine
> *
> * This routine covers the standard ARM cases: normal (0x),
> * high (0x) and VBAR. SoCs which do not
On 5 Jan 2015, feste...@gmail.com wrote:
> I noticed that mx25pdk (ARM926) does not boot anymore with top of tree
> U-boot.
>
> Doing a git bisect resulted in the following commit as being the
> guilty one:
>
> commit 3ff46cc42b9d73d01c86df904425704410958470
> Author: Georges Savoundararadj
> Da
Albert,
I guess it is too late for that now. Thought it would make it into
2015.01, since your last comment in v2 suggested that you would treat it
as bugfix...
--
Stefan
On 2014-12-18 18:10, Stefan Agner wrote:
> Resynchronize memcpy/memset with kernel 3.17 and build them in
> Thumb2 mode (unif
Hi,
I noticed that mx25pdk (ARM926) does not boot anymore with top of tree U-boot.
Doing a git bisect resulted in the following commit as being the guilty one:
commit 3ff46cc42b9d73d01c86df904425704410958470
Author: Georges Savoundararadj
Date: Tue Oct 28 23:16:11 2014 +0100
arm: relocat
On 01/05/2015 12:27 PM, Fabio Estevam wrote:
> [Adding more folks on Cc]
>
> On Mon, Jan 5, 2015 at 3:35 PM, Ian Molton wrote:
>> Hi folks,
>>
>> I'm attempting to bring up a custom board with an i.mx6q on it.
>>
>> I've added support for PCIe and E1000 ethernet, and the PCI bus scans,
>> showing
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