From: Dirk Behme
Use the boards from boards.cfg for building ./MAKEALL ARMV7.
Signed-off-by: Dirk Behme
---
Changes in v3: Instead of touching all ARMx boards, only update
ARMV7. Current LIST_ARMV7 builds 19 boards while -c armv7 (i.e. using
boards.cfg) builds 31 boards (including all boards f
- "Prafulla Wadaskar" wrote:
> > -Original Message-
> > From: u-boot-boun...@lists.denx.de
> [mailto:u-boot-boun...@lists.denx.de]
> > On Behalf Of Ajay Bhargav
> > Sent: Thursday, August 04, 2011 4:21 PM
> > To: Lei Wen
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH v
Your driver is certainly a lot cleaner than mine... mine started up as a
really hacked up SATA driver made for U-Boot 1.1.1.
I did find a number of problems, however.
I have several suggestions.
1. On many MIPS platforms (not including ours) you need to flush the cache
before write operations
On 8/5/2011 4:51 AM, Aneesh V wrote:
> Hi Albert,
>
> On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wrote:
>> Hi Aneesh,
>>
>> On 05/08/2011 12:47, Aneesh V wrote:
>>> Hi Eric,
>>>
>>> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
Hi Aneesh,
>>> [snip ..]
> IMHO, Hong's approach is
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Tim
Dear Dirk Behme,
> From: Dirk Behme
>
> Use the boards from boards.cfg for building ./MAKEALL ARMx.
>
> Note: ARM10 systems don't seem to exist any more.
Wrong: a simple grep shows that those are still in Makefile.
>
> Signed-off-by: Dirk Behme
>
> ---
> Changes in v2: Instead of dublicati
Dear Albert,
> Since this is an ARM question, I'll look into it, and since Wolfgang
> will be on vacation, I suggest either that we either postpone -rc1, or
> (preferably IMO) that we tag -rc1 now with a specific warning about the
> ARM tree, and I analyze what the issue is using several ARM too
On 13.07.2011 10:53, Minkyu Kang wrote:
> Dear Dirk Behme,
>
> On 12 July 2011 16:20, Chander Kashyap wrote:
>> On 12 July 2011 00:19, Dirk Behme wrote:
>>> From: Dirk Behme
>>>
>>> Fix compilation of mkv310_image host tool
>>>
>>> tools/mkv310_image.c: In function 'main':
>>> tools/mkv310_image.
Building the SPL for omap4_sdp4430 and omap4_panda in recent mainline
is broken due to a resulting image size > 32k:
Configuring for omap4_sdp4430 board...
arm-none-linux-gnueabi-ld: u-boot-spl section .rodata will not fit in
region .sram
arm-none-linux-gnueabi-ld: region .sram overflowed by 61
From: Dirk Behme
Using mkimage with e.g.
tools/mkimage -A arm -T firmware -O u-boot -d u-boot.bin foo.img
gives a warning
"Unknown OMAP image type - 5"
while it seems that the image itself is created successfully.
This does come from the patch "mkimage: Add OMAP boot image support".
Reorder
From: Dirk Behme
The patch "omap: reuse omap3 gpio support in omap4" moves
arch/arm/include/asm/arch-omap3/gpio.h to
arch/arm/include/asm/omap_gpio.h but misses to touch all
users of arch-omap3/gpio.h. This results in various build
failures like
: error: asm/arch/gpio.h: No such file or director
From: Dirk Behme
Use the boards from boards.cfg for building ./MAKEALL ARMx.
Note: ARM10 systems don't seem to exist any more.
Signed-off-by: Dirk Behme
---
Changes in v2: Instead of dublicating the missing boards from
boards.cfg to MAKEALL, use the boards defined in boards.cfg
directly.
MA
Timur Tabi wrote:
> Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
> macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
> This is necessary for the assembly-language code that relocates CCSR, since
> the assembler does not understand 64-bit const
Yes, that's what I mean: the code get's dropped, and then nobody ever
cares about it again. Such unmaintained code is basicly useless to
everyone, and just adds efforts that coul better be used for other
work.
> Marri (or somebody else from APM): Do you plan to support the 460SX
boards?
> Then pl
This tool takes a key=value configuration file (same as would a `printenv' show)
and generates the corresponding environnment image, ready to be flashed.
Signed-off-by: David Wagner
---
Hi Thomas,
This second version addresses all your comments except - as we discussed - the
cast vs. st
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.
CONFIG_SYS_CCSRBAR_
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure. This is
called the initial RAM area, or initram. The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overla
Hello,
Le Fri, 5 Aug 2011 16:49:58 +0200,
David Wagner a écrit :
> This tool takes a key=value configuration file (same as would a `printenv'
> show)
> and generates the corresponding environnment image, ready to be flashed.
Nice tool. I'm currently using a crappy shell-based equivalent of th
Hi Albert,
On Monday 01 August 2011 04:48 PM, Aneesh V wrote:
> c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
> to board_init_r(). This enables d-cache for all ARM boards.
> As a result some of the arm boards that are not cache-ready
> are broken. Revert this change and allow plat
Hi Albert,
On Friday 05 August 2011 06:47 PM, Albert ARIBAUD wrote:
> (BTW: responders to this thread please stop using my @free.fr address. I
> just noticed the big pile of U-Boot related messages that went to an
> account which I do not use for U-Boot any more)
>
> On 05/08/2011 13:51, Aneesh V
This tool takes a key=value configuration file (same as would a `printenv' show)
and generates the corresponding environnment image, ready to be flashed.
Signed-off-by: David Wagner
---
tools/Makefile |5 ++
tools/mkenvimage.c | 157
From: Poonam Aggrwal
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0x_) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMA
From: Poonam Aggrwal
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.
Impact:
Boot from IFC may not be successful if IFC_CS3 is used.
Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
From: Poonam Aggrwal
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.
P1010RDB Overview
-
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16b
From: Dipen Dudhat
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC. U
From: Dipen Dudhat
And various defines to enable NAND support and NAND spl code for the
P1010RDB platform.
Signed-off-by: Dipen Dudhat
Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala
---
boards.cfg|2 +
include/configs/P1010RDB.h
From: Poonam Aggrwal
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size
Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data
Workaround:
The workaround is to switch to GPCM mode for NOR Flash acc
From: Poonam Aggrwal
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.
Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Additionally remov
Patch series adds support for P1010RDB, NAND support (for IFC on P1010)
and various errata fixes for P1010.
V2 changes:
* re-work based on CCSRBAR cleanup patches
* white space fixes
* checkpatch cleanup fixes
* rework 'dummy' udelay in nand spl code
- k
__
On 05/08/2011 15:49, Linus Walleij wrote:
> This deletes the integrator split_by_variant.sh script and
> defines a number of unique board types for the core modules
> that are meaningful to support for the Integrator AP/CP, i.e.
> the ones that did not just say "unsupported core module" in
> split_
Kumar Gala wrote:
> ok. Sounds fine to leave as it, just wondering.
Also, I want people to specifically set the physical address in the board
header file if they want to relocate CCSR.
Anyway, I'll post a new version that reduces the merge conflicts.
--
Timur Tabi
Linux kernel developer at Fre
This deletes the integrator split_by_variant.sh script and
defines a number of unique board types for the core modules
that are meaningful to support for the Integrator AP/CP, i.e.
the ones that did not just say "unsupported core module" in
split_by_variant.sh. If more core modules need to be suppo
On Aug 5, 2011, at 8:11 AM, Tabi Timur-B04825 wrote:
> Kumar Gala wrote:
>> Why didn't we do in include/mpc85xx.h:
>>
>> #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
>> #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
>> #endif
>>
>> Thus removing that line from every board file?
>
> That might
Kumar Gala wrote:
> Why didn't we do in include/mpc85xx.h:
>
> #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
> #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
> #endif
>
> Thus removing that line from every board file?
That might make more sense, but that will break other boards where virtual
!= p
(BTW: responders to this thread please stop using my @free.fr address. I
just noticed the big pile of U-Boot related messages that went to an
account which I do not use for U-Boot any more)
On 05/08/2011 13:51, Aneesh V wrote:
> Hi Albert,
>
> On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wr
Hi Rajeev,
On 05/08/2011 13:48, Rajeev Rao Battu wrote:
> Greetings,
>
> I am working as an R&D Engineer. presently i am using u-boot ver
> 2008.10 and wanted to shift to latest version.
> I had downloaded 2011.06 from DENX website. when i tried to compile it its
> bit different and i
On Aug 4, 2011, at 6:03 PM, Timur Tabi wrote:
> Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
> macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
> This is necessary for the assembly-language code that relocates CCSR, since
> the assembler do
On 08/05/2011 02:19 PM, Wolfgang Denk wrote:
> Fix:
>
> include/asm/arch/clock.h:35: warning: function declaration isn't a prototype
>
> Signed-off-by: Wolfgang Denk
> Cc: Stefano Babic
> Cc: Albert ARIBAUD
> ---
Already fixed on u-boot-imx
Best regards,
Stefano Babic
--
==
On 08/05/2011 02:29 PM, Wolfgang Denk wrote:
> The Lattice code was missed by commit e6a857d "fpga: constify to fix
> build warning" resulting in such warnings:
>
> fpga.c: In function 'fpga_load':
> fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers
> from pointer targ
On Aug 4, 2011, at 8:49 PM, Aaron Williams wrote:
> Hi all,
>
> I'm working with a Silicon Image U-Boot driver that supports the SIL3124,
> 3132
> and related PCI/PCIe controllers.
>
> So far I have it working with the 3132 except when I try and make use of
> LBA48
> features. I'm not sure
The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:
fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers
from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warn
The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:
fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers
from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warn
Fix:
include/asm/arch/clock.h:35: warning: function declaration isn't a prototype
Signed-off-by: Wolfgang Denk
Cc: Stefano Babic
Cc: Albert ARIBAUD
---
arch/arm/include/asm/arch-mx31/clock.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx
Hi Albert,
On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> On 05/08/2011 12:47, Aneesh V wrote:
>> Hi Eric,
>>
>> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
>>> Hi Aneesh,
>> [snip ..]
IMHO, Hong's approach is correct. If the buffer that is invalidated is
Greetings,
I am working as an R&D Engineer. presently i am using u-boot ver
2008.10 and wanted to shift to latest version.
I had downloaded 2011.06 from DENX website. when i tried to compile it its
bit different and i am facing problems.
where can i get document of change log or any o
Le Fri, 05 Aug 2011 11:37:05 +0200,
Detlef Vollmann a écrit :
> The (maximum) size of the image to load is hardcoded into
> at91bootstrap. For most boards (including at91sam9m10g45-ek) this is
> 0x33900 if loading from DataFlash and 0x4 if loading from NAND.
>
> So if you didn't modify your
Hi Reinhard,
On 05/08/2011 13:23, Reinhard Meyer wrote:
> Dear Albert, Aneesh, Eric,
>>> We have a fundamental problem when it comes to invalidating an
>>> un-aligned buffer. Either you flush the boundary lines and corrupt your
>>> buffer at boundaries OR you invalidate without flushing and corrup
Dear Albert, Aneesh, Eric,
> > We have a fundamental problem when it comes to invalidating an
> > un-aligned buffer. Either you flush the boundary lines and corrupt your
> > buffer at boundaries OR you invalidate without flushing and corrupt
> > memory around your buffer. Both are not good! The onl
Hi Aneesh,
On 05/08/2011 12:47, Aneesh V wrote:
> Hi Eric,
>
> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
>> Hi Aneesh,
> [snip ..]
>>>
>>> IMHO, Hong's approach is correct. If the buffer that is invalidated is
>>> not aligned to cache-line, one cache-line at the respective boundary
>>> may
From: Tang Yuantian
Add the Silicon Image series PCI Express to
Serial ATA controller support, including Sil3132,
Sil3131 and Sil3124.
The SATA controller can be used to load kernel.
The features list:
- Supports 1-lane 2.5 Gbit/s PCI Express
Hi Eric,
On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
> Hi Aneesh,
[snip ..]
>>
>> IMHO, Hong's approach is correct. If the buffer that is invalidated is
>> not aligned to cache-line, one cache-line at the respective boundary
>> may have to be flushed to make sure the invalidation doesn't aff
Hi Aneesh,
On 08/05/2011 03:10 PM, Aneesh V wrote:
> Hi Hong, Albert,
>
> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>> Le 05/08/2011 08:38, Hong Xu a écrit :
>>> Hi Albert,
>>>
>>> I've tried to deal with the case that the (start, stop) is not aligned.
>>> If mis-align happens, the
Hi Albert, Wolfgang,
On Monday 01 August 2011 04:48 PM, Aneesh V wrote:
> - Avoid enabling caches for all ARM boards
> - Enable caches for omap3/4
> - Stronger barrier for armv7 cache-maintenance operations.
Do you have any more comments on this series. I tend to agree with
Jason's views about co
On 08/05/11 00:12, Thomas Petazzoni wrote:
> However, I have just taken an AT91SAM9261-EK and it seems that U-Boot
> from atmel/master does not work at all.
>
> First, the AT91Bootstrap binary provided by Atmel only loads 0x33900
> bytes from the Dataflash, but current U-Boot binaries are larger th
Hi Albert,
On Friday 05 August 2011 02:50 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> On 05/08/2011 09:10, Aneesh V wrote:
>> Hi Hong, Albert,
>>
>> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>>> Le 05/08/2011 08:38, Hong Xu a écrit :
Hi Albert,
I've tried to deal with
Hi Aneesh,
On 05/08/2011 09:10, Aneesh V wrote:
> Hi Hong, Albert,
>
> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>> Le 05/08/2011 08:38, Hong Xu a écrit :
>>> Hi Albert,
>>>
>>> I've tried to deal with the case that the (start, stop) is not aligned.
>>> If mis-align happens, the adj
On 08/03/2011 12:05 PM, Jason Liu wrote:
> CONFIG_L2_OFF is obsolete after the following commit:
>
> e47f2db5371047eb9bcd115fee084e6a8a92a239
> armv7: rename cache related CONFIG flags
> Replace the cache related CONFIG flags with more meaningful
> names. Following are the changes:
> CONFIG_L2_OFF
Hi Simon,
On Tuesday 02 August 2011 09:29 PM, Simon Schwarz wrote:
> Implements the saving of boot params passed by OMAP3 ROM code.
>
> Signed-off-by: Simon Schwarz
> ---
> Didn't exist before V8
> ---
> arch/arm/cpu/armv7/omap-common/spl.c |6 +-
> arch/arm/cpu/armv7/omap3/lowlevel
Hi Simon,
Sorry if my response is late. I was not in office for couple of days.
On Tuesday 02 August 2011 09:29 PM, Simon Schwarz wrote:
> Add NAND support for the new SPL structure.
>
> Signed-off-by: Simon Schwarz
> ---
> This patch didn't exist before V2!
>
> V2 changes:
> ADD Some define-barr
Hi Hong, Albert,
On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
> Le 05/08/2011 08:38, Hong Xu a écrit :
>> Hi Albert,
>>
>> I've tried to deal with the case that the (start, stop) is not aligned.
>> If mis-align happens, the adjacent lines will be cleaned before
>> invalidating. And fro
On 08/05/2011 02:46 PM, Albert ARIBAUD wrote:
> Le 05/08/2011 08:38, Hong Xu a écrit :
>> Hi Albert,
>>
>> On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
>>> Hi Hong Xu,
>>>
>>> Le 05/08/2011 06:44, Hong Xu a écrit :
After DMA operation, we need to maintain D-Cache coherency.
We need to cl
61 matches
Mail list logo
