e top 4 bits of flag
aren't writeable, and the docs say they always read as '1', so I presume
any value in that register will be 0b when saved to the stack.
An interesting thought experiment nonetheless.
Regards,
Basil Hussain
_
need these snippets of inline assembly.
Is there any scope for changing the PDK code generation to use
t1sn.io/t0sn.io?
Regards,
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t you'd have to reset it back to zero before it is used
by any SDCC-generated code. So you'd have to disable interrupts before
using the byte (and then reeenable them again after zeroing the byte).
Yes, precisely. I hadn't thought about interrupts attempting to use P,
thanks
kay to use the upper byte of P for arbitrary purposes, so long as that
byte is always reset back to zero afterwards?
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er?
Functions always return using 'ret' instruction? That is, no 'goto'
shenanigans?
Are there any differences between PDK13, 14, 15?
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d
well at most conditions", which, apart from other issues discussed
within the ticket, hindered the proper application of the submitter's
rules too.
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ll do that.
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2
set0.io __intrq, #2
00103$:
pop af
mov p, a
pop af
reti
You can see that for the lines following those that would match the
first rule, no matter which branch is taken, the first use of A reg is
to have something assigned to it
On 18/12/2022 11:14, Daniel Drotos wrote:
Can you send me hex of your two compiled test programs, A and B, please?
I have sent you a hex file off-list.
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is an undocumented switch as far
as I can see.
Also, what is the difference between setting "sim_run=1" and the "run"
command? Surely the latter should do what it says regardless of context?
Regards,
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int stopping execution and the last command in
the breakpoint script being "run"? It seems to actually process the
"run", as evidenced by the "Simulation started..." line, but stops
regardless.
Regards,
Basil Hussain
ces in measured cycles from? I
seem to recall that although cycle counts for some STM8 instructions
were incorrect in older SDCC releases, they had been corrected quite a
while ago - are some still incorrect? This is with uCsim 0.6.4 from SDCC
4.2.0.
Regards,
Basil Hussain
_
n 'foo' is in fact a __naked inline assembly function, where I am
not cleaning the function arguments from the stack.
Regards,
Basil Hussain
P.S. By the way, now I am looking at the manual again, is there not a
mistake in section 4.5.1.2 describing calling convention version 0? It sa
ing to mitigate by
rearranging my code in all sorts of ways, yet I cannot convince SDCC to
emit the proper stack clean-up code for the affected function call.
Anyone have any advice?
Regards,
Basil Hussain
P.S. SDCC version:
SDCC :
mcs51/z80/z180/r2k/r2ka/r3ka/sm83/tlcs90/ez80_z80/z80n/ds
re the strings directly in the array. But I fear
I might end up having to do this if this duplicated strings problem is
unresolvable.
Regards,
Basil Hussain
P.S. SDCC version:
SDCC :
mcs51/z80/z180/r2k/r2ka/r3ka/sm83/tlcs90/ez80_z80/z80n/ds390/pic16/pic14/TININative/ds400/hc08/s08/stm8/pdk13/pdk
If zero, return false. Otherwise, mask out
'up' bit to set it to false, and return true.
Where is the supposed change in conditional flow? It seems to be warning
about nothing.
Regards,
Basil Hussain
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willing to file one on his behalf.
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');
ld a, (0x01, sp)
add a, #0x30
pop a
jp _disp_putc
00101$:
; foo.c: 18: }
pop a
ret
My SDCC version:
SDCC :
mcs51/z80/z180/r2k/r2ka/r3ka/sm83/tlcs90/ez80_z80/z80n/ds390/pic16/pic14/TININative/ds400/hc08/s08/stm8/pdk13/pdk14/pdk15/mos6502
4.
calling convention, then
this doesn't help, but I thought this approach was the most expedient
for getting existing inline assembly code compiling with 4.2.0+.
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of
the DIV workaround in their ISRs for no real reason.
But then if you're that concerned about performance, you would be
looking at the output assembly anyway, and discover it - like I was. :)
Regards,
Basil Hussain
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b-call to ___memcpy() - but I
don't see why that would ever be using a DIV/DIVW instruction.
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on, which I don't want to happen, so I'd prefer if there was
some other way.
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x27;t make any provision for code written in C, I don't know how
relevant it may be for people looking for solutions in that context.
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atic C
variables with whatever assembly symbol is associated with it. I always
feel dirty relying on the informal implementation detail of SDCC making
assembly symbols the same as the variable name prefixed with an
underscore (e.g. "foo" => "_foo").
Regards,
Basil Huss
ck of 512 bytes on their memory map, so one could
assume that they behave the same as the STM8S/AF. But, without parts in
hand to actually test, who really knows...
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h
cally roll over". Because, I
guess, thinking about it, what would be the point of the latter?
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overwrite existing data?
Do you know which STM8 parts these are that have a limit but do not have
roll-over?
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M0016,
section 3.1.2 "Stack handling" has a note on Figure 4 saying "The stack
roll-over limit is not implemented on all devices". I'm not actually
aware of any STM8 devices that _don't_ have a stack limit. Does anybody
know of any t
2 and pop1/pop2 macros (in stm8mac.h) appear to simply
decrement/increment in an unbounded manner, and may not implement any SP
wrapping.
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::Blocks, 20.03, I am maintaining a version of the compiler options
file compatible with that (the version currently in C::B trunk is
incompatible) in a GitHub repository:
https://github.com/basilhussain/codeblocks-sdcc-options.
Regards,
Basil Hussain
Question: for options that don't work on all ports, are they silently
ignored, or will SDCC give an error?
No. It will give a warning.
Okay, that's good. It means if a user selects an option which doesn't
apply to their target architecture, they'll know about it as soon as
they attempt to
gt;
Not sure if this works for all ports.
Guess I could remove it then, as it's a pretty specialised and probably
very rarely used option. Question: for options that don't work on all
ports, are they silently ignored, or will SDCC give an error?
Regards,
Basil Huss
.
Regards,
Basil Hussain
P.S. If it aids comprehension, a reference of Code::Blocks compiler
options syntax can be found here:
https://wiki.codeblocks.org/index.php/Compiler_options_file
Also adding the newer options for C2x and others
such as --sdcccall.
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Basil Hussain
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On 24/02/2022 18:33, Philipp Klaus Krause wrote:
Looks like a bug to me. Please file a bug report.
Thanks for confirming. I have filed a bug report:
https://sourceforge.net/p/sdcc/bugs/3332/
Regards,
Basil Hussain
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Sdcc
whether prologue and epilogue
code inside that function is generated.
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ly how the function
is to be called by other code, but also affects how SDCC generates code
to access args within the function.
Regards,
Basil Hussain
P.S. There is a minor error in the user manual in section 4.5.1.2. The
second sentence begins "The stack is the stack is not adjusted for
foo.s' and the output object file linked as per normal.
If anyone has an questions, feel free to ask. :)
Regards,
Basil Hussain
P.S. In case you're wondering why I needed this, it's because I was
experimenting with self-modifying assembly
I have created a feature request:
https://sourceforge.net/p/sdcc/feature-requests/756/
Included there is a test program to demonstrate the issue.
If I have time, and I can get my SDCC build environment going again, I
may try to fix it myself and submit a patch.
Regards,
Basil Hussain
On
plementation defined", but I think this should be fixed.
Shall I create a feature request? Or a bug report?
Regards,
Basil Hussain
On 10/11/2021 22:38, Basil Hussain wrote:
Hi all,
Quick question: was the SDCC standard library printf() implementation
for the %p conversion specifier
arget platforms such as the STM8.
Whenever you use %p, the pointer value is formatted with the bytes in
the wrong order. For example, a pointer with value of 0x87A1 is output
as "0xa187". It's annoying to have to mentally transpose the bytes when
looking at debugging output.
Re
. :)
Regards,
Basil Hussain
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gument for displaying .define substitutions in
source listings?
Regards,
Basil Hussain
On 30/10/2021 16:32, Basil Hussain wrote:
Hi all,
Does the version of AS used for SDAS assemblers not support
.define directives?
I am tearing my hair out trying to figure out if it doesn't actually
than when forked, but the .define
directive (and it's siblings, .undefine, .ifdef, .ifndef, etc.) is
actually mentioned in the SDAS docs that are included with SDCC.
So what is going on here?
Regards,
Basil Hussain
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t
thing is some stdlibs having a strrev().
Regards,
Basil Hussain
Disclaimer: I have written an optimised assembly library for STM8 that
covers most of the mentioned functionality:
https://github.com/basilhussain/stm8-utils. So my opinions may be
slightly biased... :)
On 03/10/2021 08:57, Phil
sters
were not in their original state when returning to ROM code.
Regards,
Basil Hussain
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mory model, stack cleanup for stack parameters is
done by the calle for some cases
Typo obscures understanding here: is that supposed to be "caller" or
"callee"?
Regards,
Basil Hussain
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s section of the manual
explicitly stated whether each pragma can be saved and restored.
Regards,
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#0x02
ld %1+%3, a
} by {
bset %1+%3, #1
} if notUsed('a'), notUsed('n'), notUsed('z'), operandsLiteral(%3)
The rule would need to be repeated to cover every bit position - e.g.
#0x01, #0x02, #0x04, etc. for 'or' instruction
developed - see
https://github.com/basilhussain/stm8-bootloader-erase-write/blob/main/src/check-seg-size.awk.
I know I am missing something, but what is it?
You're missing that the options you tried don't exist or don't have any
effect on the target platform
On 12/12/2020 16:26, Philipp Klaus Krause wrote:
The code is correct, so it's not a bug. I suggest to file a feature
request instead.
Okay. I have filed feature request #728.
Basil
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rate
different formatting for what ends up as the same instruction. Like I
said earlier, it makes writing peephole optimiser rules needlessly
difficult when there are such inconsistencies. Is it worth filing a bug
report to address this?
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rOf, but
the second case does not.
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t;ldw x, #(%1 + %3)", and one to match
"ldw x, #%1+%3", which is a whole lot of duplication for no good reason.
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I noticed it
wasn't working.
Any particular reason why callee-saves has not been implemented for STM8?
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s wouldn't happen to be one of those SDCC features that is
8051-specific, but not documented as such?
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Basil Hussain
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On 04/12/2020 09:43, Philipp Klaus Krause wrote:
There are newer builds on the snapshot page (usually about one day
behind current trunk in svn), including Windows binaries:
Oh, of course, I forgot about those. Thanks for reminding me.
I will try the latest snapshot ucSim and see if it solves
On 04/12/2020 07:25, Daniel Drotos wrote:
I'll try to test it. You mentioned "io ninja", I'll intall it. How do
you create pipes with it?
I've only recently started using IO Ninja myself, so I'm certainly no
expert on it, but I played with the Pipe Server functionality:
File > New Session >
On 03/12/2020 19:28, Daniel Drotos wrote:
I do not have too much experience with windows, but on unix, this is
normal. This is the behavior of the pipe, not the app. When first
program opens one end of the pipe, it will be blocked by the OS. It
waits to open other end. You have to start a progr
ve first tried to type anything in the ucSim
console, and then send data to the pipe, it makes what I typed appear,
but the console is still unresponsive.
It seems like the console is blocked, and piping data somehow
temporarily causes it to be unblocked.
Any ideas? Is this a bug in ucSim?
Re
w
disassembly, it doesn't look like that. Maybe some global variable is
used - the code certainly reads and writes several locations in the
0x80-0x90 area.
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Basil Hussain
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ut from compilation? Or
maybe the Hex file?
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ably getting some garbage
value from the stack as an argument and going in to an infinite loop or
some other unexpected behaviour, and not blinking the LED.
Try instead substituting value of "-j" arg with whatever address main()
is actually at - check the .map file after linking.
Regard
l be,
so maybe that's not a problem given the S208's specification of 10k
write cycles. But it would be suicide on smaller chips, like the
STM8S003, where flash is only specified for 100 (yes, one hundred) write
cycles.
Regards,
Basil Hussain
SINIT
segment with a command line argument: "-Wl-bGSINIT=0x8080".
Regards,
Basil Hussain
On 18/11/2020 22:10, Karsten Langeloh wrote:
Hello everyone,
no this is not the "how do i do interrupts with sdcc" question :)
I have used sdas-stm8 in the past to convert some &q
I figured something out. I think my problems were mostly down to the
fact I was using a literal value as argument to the macro (e.g. "foo
6"). The assembler is not creating a new variable 'n' inside the macro,
it is just substituting the argument in place of 'n'. So, of course,
where there is "
; ...etc...
ld a, #0
adc a, (0, sp)
ld (0, sp), a
Anyone know how to do this?
Regards,
Basil Hussain
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I sat down this afternoon to take a look at seeing if I could myself
make the modifications to ucSim to add better cycle counting by adding
tick() calls...
But after updating from SVN, configure, make, etc. I ran a little test
case with some assembly with multi-cycle instructions and was very
Would it be much effort to implement a simplified version, i.e. ignoring
pipelining, just counting a fixed number of cycles per instruction?
Is it not just a case of ensuring that calls to tick() with appropriate
argument value are implemented in the right places? Specifically, all
the inst
It needs some work to make it more realistic.
Yes. I was looking at the source code just now (stm8.src/stm8.cc and
stm8.src/inst.cc) and it seems clock cycles are incremented by use of a
tick() function call. All instructions appear to be assumed as taking 1
cycle by default, with addition
Nowhere, and nothing defines that. Correct tick counting is not
implemented in uCsim (except s51). It counts 1 clock (tick) for every
instruction which will be unreal especially when lot of jumps happen.
Oh, I don't expect ucSim to fully and exactly replicate STM8 behaviour,
including pipel
Yes, I am aware that the STM8 has a pipelined architecture. I don't
think that this can be wholly explained by that.
Let me provide some context. My benchmark for my strcpsn implementation
performs 1000 iterations of the following:
strcspn("1620376B3653",
"abcdefghijklmnopqrstuvwxyzABCDEFGHI
x27;t used elsewhere.
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Basil Hussain
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Feature request, not bug, as the generated code is correct.
Ah, yes, that's true. Sorry. Thanks for moving the ticket.
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I have covered all the bases with
the conditions/restrictions.
Regards,
Basil Hussain
On 15/07/2020 20:21, Philipp Klaus Krause wrote:
I'd suggest to open a ticket item if there is none yet.
With the peephole rules and code samples to reproduce the inefficient
code. Maybe part of it can
had to repeat some rules. Although, it seems the
existing bset/bres/bcpl rules do this too, so maybe it's not actually
possible to make the transformation.
One other thing to note is that I figured it's not worth bothering to
optimise ld+jrmi/jrpl to btjt/btjf (used when testing bit 7) because
they are same number of cycles and bytes.
Regards,
Basil Hussain
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he later
'pg90' table? 0x5A in that also gives a value of 2.
Are these the correct locations?
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document says (pg. 100) that this
instruction takes 1 cycle. ucSim also runs DECW in a single cycle, which
agrees with the docs.
Which is correct?
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https
ge for its type", and some to do with
trigraph operators.
Given this, can I be 100% confident that my modifications are
successful? I will create and submit a patch if so.
Regards,
Basil Hussain
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.
What was puzzling was that even doing a "make clean" didn't solve the
problem, because for some reason that doesn't delete the end-product of
the build, the .lib file, like one might expect it to.
Running the regression tests again now, so far without warnings...
Re
ines
referencing either the library name ("stm8" vs "stm8-large") or the SDCC
command line (addition of "--model-large"). The only (single) mention of
"strcmp" and "strcpy" is in the OBJ definition, where .rel files with
those names
at now have assembly implementations will no longer be
included in the lib. That is, change the STM8_INT, STM8_LONG,
STM8_LONGLONG and OBJ definitions to match the non-large lib's Makefile.in.
If I have modified only the lib's Makefile.in, how do I then re-generate
the Make
oes this sound correct? Any other 'gotchas'?
I am thinking I will try to copy and convert the code for use in the
'large' STM8 library and create a patch. If I do so, how can I test that
my changes are working correctly? Can the regression tests do this? If
so, how do I run
uch slower after I
compiled it with --model-large. Now I know why...
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Basil Hussain
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of a
register ('0x...'), which would preclude the whole rule!
I implemented the optimization in code generation:
https://sourceforge.net/p/sdcc/code/11643/
That's awesome, thanks very much!
Regards,
Basil Hussain
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page_enum_t is:
typedef enum {
CAN_PG_TX_MBOX_0 = 0,
// ...
CAN_PG_RX_FIFO = 7
} can_page_enum_t;
CAN_PSR is defined as: #define CAN_PSR (*(volatile uint8_t *)(0x5427))
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('a')
Does the rule need anything else? Something to assert that the %1 and %2
source/destination addresses are 'longmem' (or 'shortmem')? Some way of
determining if any following instructions rely on N/Z flags (e.g. JRNE)?
Regards,
Basil Hussain
P.S. I als
It is quite painful to interpret sometimes. I find that it
makes too many assumptions that the user is running the 8051 simulator,
barely acknowledges the other platforms it supports, and as I already
mentioned, some commands are completely undocumented. Hopefully this can
be rectified in future.
Yes, I am aware of that. Like I already said, I have basic simif
interface functionality working - I can use the 'detect' command and get
back the proper response, as well as other commands.
What I am interested in is how to access this information:
Configuration memory of simif
0x00 0001
uint32_t val;
uint8_t raw[4];
} pc;
UCSIM_IF = 0x0C;
pc.raw[0] = UCSIM_IF;
pc.raw[1] = UCSIM_IF;
pc.raw[2] = UCSIM_IF;
pc.raw[3] = UCSIM_IF;
Can anyone tell me how I am supposed to read the simif configuration values?
Regards,
Basil Hussain
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On 20/05/2020 05:30, Sebastian Riedel wrote:
It’s integer promotion.
Ah, yes, I see it now. Some sort of sign-extension. But it still doesn't
make any sense to me.
I tried compiling with --no-peep, to see if the optimiser was removing
anything that would put the extraneous code in context,
Here's a self-contained example that I can replicate the issue with:
#include
uint8_t foo(uint16_t value) {
return value;
}
uint8_t bar(uint16_t value) {
return (value ? foo(value) + 1 : 0);
}
void main(void) {
uint8_t x = bar(0xFF);
}
Compiled with:
sdcc.exe -mstm8 --std-c99 -I"C:\
ct.
uint8_t ffs_16(uint16_t value) {
uint8_t idx = 0;
if(value) idx = ctz_16(value) + 1;
return idx;
}
Regards,
Basil Hussain
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quot;C:\Program Files\SDCC\bin\..\include" "main.c"
sdcc: Generating code...
sdcc: Calling assembler...
sdcc: sdasstm8.exe -plosgffwy ""obj\IHX\main".asm"
sdcc: Calling linker...
sdcc: sdldstm8.exe -nf ""bin\IHX\test.lk""
I am using SDCC 4.0.0
te:
Am 25.04.20 um 08:27 schrieb Basil Hussain:
Hi all,
Are there any predefined macros that indicate what level of optimisation
SDCC is compiling with?
No. Feel free to open a feature request
(https://sourceforge.net/p/sdcc/feature-requests/).
Philipp
_
Hi all,
Are there any predefined macros that indicate what level of optimisation
SDCC is compiling with?
I have some inline assembly where I'd like to unroll a loop if
'--opt-code-speed' optimisation is being used. Or maybe the opposite: a
non-unrolled loop only if --opt-code-size is being u
stions for
improvement.
Thanks,
Basil Hussain
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Okay, I am confused now...
I can probably solve the particular instance of this non-optimisation
by removing the "push a" and "pop a" pro/epilogue from my inline
assembly, as the following C code does not rely on A being maintained.
But I am hesitant to do so, concerned that I may inadvertentl
Hi,
the use of inline assembly may lead to the optimizer being extra /
overly careful. I'm not sure if the peephole optimizer looks into the
resulting inline assembly or if it just sees a black box labeled
"inline assembly inside" and assumes the worst: 'a' is read in there.
Will it be extra
Hi all,
Sometimes, for reasons unclear to me, SDCC's optimiser fails to
optimise simple C statements doing register bit set/clear operations
in to the appropriate STM8 bset/bres instructions.
Here's the example I noticed today. The C code, and the ASM it became:
FLASH_NCR2 &= ~(1U << FLASH_N
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