Reviewed-by: Greg Bellows
On 12 September 2014 21:29, Edgar E. Iglesias
wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 19 ++-
> target-arm/helper.c | 35 ++
Reviewed-by: Greg Bellows
On 12 September 2014 21:29, Edgar E. Iglesias
wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper-a64.c| 1 +
>
Reviewed-by: Greg Bellows
On 12 September 2014 21:29, Edgar E. Iglesias
wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper-a64.c| 1 +
> target-arm/helper.c|
Is it necessary to make SCR 64-bit if it is 32-bit on both v7 and v8?
On 25 September 2014 13:15, Peter Maydell wrote:
> On 13 September 2014 05:29, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h| 19
Thanks for the clarification.
On 25 September 2014 14:53, Peter Maydell wrote:
> On 25 September 2014 20:49, Greg Bellows wrote:
> > Is it necessary to make SCR 64-bit if it is 32-bit on both v7 and v8?
>
> See previous round of reviews -- all AArch64 system registers
> ar
From: Fabian Aggeler
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm
From: Sergey Fedorov
...from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4
Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Added reset value on SCR_EL3
- Squashed SCR Migration fix (previously patch 33)
This patch adds code to mark duplicate CP register registrations as
NO_MIGRATE to avoid duplicate migrations.
v3 -> v4
- Renamed security_cp_regi
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 18 +-
target-arm/helper-a64.c| 6 +++---
target-arm/helper.c| 22
banked
target-arm: make IFAR/DFAR banked
target-arm: make PAR banked
target-arm: make VBAR banked
target-arm: make c13 cp regs banked (FCSEIDR, ...)
target-arm: add cpu feature EL3 to CPUs with Security Extensions
Greg Bellows (3):
target-arm: rename arm_current_pl to arm_current_el
tar
: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Merge with v4 patch 10
---
target-arm/cpu.h | 116 ++-
1 file changed, 106 insertions(+), 10 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c000716..30f5
From: Fabian Aggeler
Implements SMC instruction in Aarch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Merge pre_smc upstr
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
From: Fabian Aggeler
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Simplify target EL function including remo
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5be258b..f7148d1 100644
--- a
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use renamed arm_current_el()
---
target-arm/cpu.h|
different TCG code depending on
CPU secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Merge changes
- Fixed issue where TB secure state flag was incorrectly being set based on
secure state rather than NS setting. This cau
From: Fabian Aggeler
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and
checking for the existence of EL3 and non-existence of EL2.
---
target-arm/helpe
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Added use of ARM CP secure/non-secure bank flags during regis
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c| 2 +-
target-arm/cpu.c | 5 +--
target-arm/cpu.h | 13 +++-
target-arm/helper.c| 85
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take
secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the
A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (Aarch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead
of the A32_BANKED macro. T
From: Fabian Aggeler
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 21 +--
target-arm/helper.c | 58
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Fix par union/structure definition
---
target-arm/cpu.h|
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
v3 -> v4
- Fix vbar union/struct
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination w
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 nam
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files
Added the ability to print the scr register like can be done with the cpsr.
Signed-off-by: Greg Bellows
---
gdb-xml/arm-core.xml | 1 +
target-arm/cpu.c | 2 +-
target-arm/cpu.h | 2 ++
target-arm/gdbstub.c | 3 +++
target-arm/helper.c | 5 +
5 files changed, 12 insertions(+), 1
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed c2_mask updates to use the TTBCR cp
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v3 -> v4
- Fix tpidrprw mapp
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 6 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1fa9e0d..7a8eaef 100644
--- a
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ea2169b..2a0eeb3
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14
From: Fabian Aggeler
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed c2_mask updates to use the TTBCR cp
Yeah, that would be cleaner, I'll fix it in the next version.
On 30 September 2014 17:50, Edgar E. Iglesias
wrote:
> On Tue, Sep 30, 2014 at 04:49:14PM -0500, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > arm_is_secure() function allows to determine CPU sec
Yes. Done for next version.
On 30 September 2014 17:56, Edgar E. Iglesias
wrote:
> On Tue, Sep 30, 2014 at 04:49:16PM -0500, Greg Bellows wrote:
> > Renamed the arm_current_pl CPU function to more accurately represent
> that it
> > returns the ARMv8 EL rather than ARMv7 PL.
at 04:49:34PM -0500, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
> > translation functions to use TCR/TTBCR instance depending on CPU state.
> >
> > Signed-off-by: Fab
I have fixed-up some of the bank definitions and names so they more
accurately match the ARMv8 mappings. In next version.
On 30 September 2014 16:49, Greg Bellows wrote:
> From: Fabian Aggeler
>
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> FCSEIDR
Yes, good catch. Fixed in next version.
On 30 September 2014 20:23, Sergey Fedorov wrote:
> On 30.09.2014 14:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
> > Increase MMU modes since mm
Fixed in v6.
On 30 September 2014 16:49, Greg Bellows wrote:
> From: Fabian Aggeler
>
> Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
> index 7).
>
> Signed-off-by: Fabian Aggeler
> Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Greg Bell
On 6 October 2014 09:56, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > arm_is_secure() function allows to determine CPU security state
> > if the CPU implements Security Extensions/EL3.
> > arm_is_secur
On 6 October 2014 10:10, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > Renamed the arm_current_pl CPU function to more accurately represent
> that it
> > returns the ARMv8 EL rather than ARMv7 PL.
>
Comment added in v6.
> >
>
On 6 October 2014 15:07, Peter Maydell wrote:
> On 6 October 2014 20:45, Greg Bellows wrote:
> > On 6 October 2014 09:56, Peter Maydell wrote:
> >> I checked your git tree and we don't actually use
> >> arm_is_secure_below_el3() anywhere except in
> >>
On 6 October 2014 10:34, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
> > Increase MMU modes since mmu_index is directly infered from arm
On 6 October 2014 10:46, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Implements SMC instruction in Aarch32 using the A32 syndrome. When
> executing
> > SMC instruction from monitor CPU mode SCR.NS bit i
On 6 October 2014 10:53, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > This patch extends arm_excp_unmasked() according to ARM ARMv7 and
> > ARM ARMv8 (all EL running in Aarch32) and adds comments.
>
> &
On 6 October 2014 11:02, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Adds a dedicated function for IRQ and FIQ exceptions to determine
> > target_el and mode (Aarch32) according to tables in A
:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > If EL3 is in Aarch32 state certain cp registers are banked (secure and
> > non-secure instance). When reading or writing to coprocessor registers
> > the following macros can be used.
> >
> > - A32_B
On 6 October 2014 13:10, Sergey Fedorov wrote:
> On 06.10.2014 09:13, Peter Maydell wrote:
> > On 30 September 2014 22:49, Greg Bellows
> wrote:
> >> From: Sergey Fedorov
> >>
> >> This patch is based on idea found in patch at
> >&
On 6 October 2014 11:19, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Prepare ARMCPRegInfo to support specifying two fieldoffsets per
> > register definition. This will allow us to keep one register
> >
Dropped in v6
On 6 October 2014 11:27, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > Added the ability to print the scr register like can be done with the
> cpsr.
> >
> > Signed-off-by: Greg Bellows
>
> Not sure you can just arbitrari
On 6 October 2014 11:25, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > Prepare for cp register banking by inserting every cp register twice,
> > once for secure world and once for non-secure world.
> >
Converted in v6
On 7 October 2014 01:54, Peter Maydell wrote:
> On 7 October 2014 05:02, Greg Bellows wrote:
> > Right, we need the macros to do string concatenation so they have to be
> > macros. That combination occurs 3 times from a quick look. I agree
> that it
> &
On 7 October 2014 02:12, Peter Maydell wrote:
> On 7 October 2014 06:06, Greg Bellows wrote:
> >
> >
> > On 6 October 2014 11:19, Peter Maydell wrote:
> >>
> >> On 30 September 2014 22:49, Greg Bellows
> wrote:
> >> > From: Fabian
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 2 +-
> target-arm/helper.c | 8
> 2 files changed, 9 insertions(+), 1 deletion
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 2 +-
> target-arm/helper.c | 6 ++
> 2 files changed, 7 insertions(+), 1 deletion
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> No functional change.
> Prepares for future additions of the EL2 and 3 versions of this reg.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 35 +++
> target-arm/helper.c | 27 +++
> 2 files changed, 62 insertions(+)
>
> diff --git a/tar
On 11 June 2014 10:48, Greg Bellows wrote:
>
>
>
> On 9 June 2014 10:04, Edgar E. Iglesias wrote:
>
>> From: "Edgar E. Iglesias"
>>
>> Signed-off-by: Edgar E. Iglesias
>> ---
>> target-arm/cpu.h| 35 +
77,14 @@ void switch_mode(CPUARMState *env, int mode)
> env->spsr = env->banked_spsr[i];
> }
>
> +/*
> + * Determine the target EL for a given exception type.
> + */
> +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
> +{
> +return 1;
> +}
> +
>
Unless this is just a preparation to make the non CONFIG_USER_ONLY version
of this different, this can be moved out of the ifdef and made common.
> static void v7m_push(CPUARMState *env, uint32_t val)
> {
> CPUState *cs = CPU(arm_env_get_cpu(env));
> --
> 1.8.3.2
>
>
Otherwise...
Reviewed-by: Greg Bellows
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> cpu-exec.c | 5 ++---
> target-arm/cpu.h | 16
> 2 files changed, 18 insertions(+), 3 de
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Not all exception types update both FAR and ESR.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/helper-a64
Called out possibly missing fix below. Beside it, I'm convinced this
change is beneficial, other than maybe for readability.
The change does not account for uses of the affected calls in
target-arm/translate.c. As well, the change has somewhat a ripple effect
as certain code expects to receive o
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper-a64.c| 1 +
> target-arm/helper.c| 28 +++-
> target-arm/helper.h| 1 +
>
rm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1452,6 +1452,16 @@ static void disas_exc(DisasContext *s, uint32_t
> insn)
> gen_helper_hvc(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> break;
> +case 3:
> +if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->current_pl ==
> 0) {
> +unallocated_encoding(s);
> +break;
> +}
> +tmp = tcg_const_i32(syn_aa64_smc(imm16));
> +gen_a64_set_pc_im(s->pc);
> +gen_helper_smc(cpu_env, tmp);
> +tcg_temp_free_i32(tmp);
> +break;
> default:
> unallocated_encoding(s);
> break;
> --
> 1.8.3.2
>
>
Otherwise...
Reviewed-by: Greg Bellows
"not convinced" ... I was just saying that I could not find any benefit for
it.
On 11 June 2014 16:05, Peter Maydell wrote:
> On 11 June 2014 20:19, Greg Bellows wrote:
> > Called out possibly missing fix below. Beside it, I'm convinced this
> change
> > is
Reviewed-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 12
> target-arm/helper.c | 13 +
> 2 files changed, 25 insertions
Acked-by: Greg Bellows
On 9 June 2014 10:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> cpu-exec.c | 12
> target-arm/cpu.c| 20 ++--
>
Hi Sergey,
I think I am missing your point. In patch 6 arm_current_pl calls
arm_is_secure. Can you elaborate?
Greg
On 11 June 2014 07:17, Sergey Fedorov wrote:
> On 11.06.2014 03:54, Fabian Aggeler wrote:
> > arm_is_secure() function allows to determine CPU security state
> > if the CPU imp
wrote:
> Hi Greg,
>
> I'm sorry, I wasn't thoughtful enough and missed that.
> I would just suggest to combine that functions since they have a common
> part, i.e.:
>
> if (arm_feature(env, ARM_FEATURE_EL3)) {
> ...
>
> What do you think?
Conflict with Edgar's changes around the name of the security register
group v8_el3_cp_reginfo vs. security_cp_reginfo.
Given that there is a difference between the v7 regs and their v8
equivalents such as encoding, I propose we create 2 separate groups, but
map them to the same storage where appl
Missing case where it is UNPREDICTABLE to enter FIQ mode from non-secure
state if NSACR.RFR is 1.
On 10 June 2014 18:54, Fabian Aggeler wrote:
> From: Sergey Fedorov
>
> ...from non-secure state.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/helper.c |
This should be squashed with 9/32.
On 10 June 2014 18:54, Fabian Aggeler wrote:
> If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
> all exception levels other than EL3 if SCR.{FIQ|IRQ} is
> set to 1 (routed to EL3).
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h | 98
> +
On 10 June 2014 18:54, Fabian Aggeler wrote:
> Adds a dedicated function for IRQ and FIQ exceptions to determine
> target_el and mode (Aarch32) according to tables in ARM ARMv8 and
> ARM ARM v7.
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h| 3 ++
> target-arm/helper.c | 137
On 10 June 2014 18:54, Fabian Aggeler wrote:
> bits when modifying CPSR.
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/helper.c | 42 +++---
> 1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
>
On 10 June 2014 18:54, Fabian Aggeler wrote:
> Implements NSACR register with corresponding read/write functions
> for ARMv7 and ARMv8.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h| 6 +
> target-arm/helper.c | 68
> +++
On 10 June 2014 18:55, Fabian Aggeler wrote:
> Prepare ARMCPRegInfo to support specifying two fieldoffsets per
> register definition. This will allow us to keep one register
> definition for banked registers (different offsets for secure/
> non-secure world).
>
> Signed-off-by: Fabian Aggeler
>
I just wanted to point out that the change from array-notation to hard-code
numbers in the names undoes Edgar's EL2/EL3 changes. I prefer this way
over the array notation.
On 10 June 2014 18:55, Fabian Aggeler wrote:
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> DFSR h
On 10 June 2014 18:55, Fabian Aggeler wrote:
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> VBAR has a secure and a non-secure instance, which are mapped to
> VBAR_EL1 and VBAR_EL3.
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h| 12 +++-
> ta
On 10 June 2014 18:55, Fabian Aggeler wrote:
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> PAR has a secure and a non-secure instance.
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h| 10 +-
> target-arm/helper.c | 25 ++---
>
Public bug reported:
During attempts to bring-up QEMU 64-bit ARM support I discovered a
kernel panics that only occur on Windows but work properly on Linux.
The issue can be reproduced by running the following command line:
$ ./arm-softmmu/qemu-system-arm -M versatilepb -kernel
$IMAGES/vmlinuz-3
Reviewed-by: Greg Bellows
On 17 June 2014 03:45, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 36
> target-arm/helper.c | 26 +
Reviewed-by: Greg Bellows
On 17 June 2014 03:45, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 16 +++-
> target-arm/helper.c | 31 ++-
> 2 fil
Reviewed-by: Greg Bellows
On 17 June 2014 03:45, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper-a64.c| 1 +
> target-arm/helper.c|
I didn't get "[PATCH v3 13/16] target-arm: A64: Emulate the HVC insn" in
email, so I reviewed it in patchwork. No apparent changes from v2.
Reviewed-by: Greg Bellows
[v3,13/16] target-arm: A64: Emulate the HVC insn
On 17 June 2014 03:45, Edgar E. Iglesias wrote:
> From:
I agree, if we are going to allow for EL-based array indexing then the
indices should correspond to the actual EL for clarity.
I am fine with the above compromise.
On 17 June 2014 01:12, Edgar E. Iglesias wrote:
> On Fri, Jun 13, 2014 at 05:06:15PM -0500, Greg Bellows wrote:
> > I ju
On 10 June 2014 18:55, Fabian Aggeler wrote:
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
> and a non-secure instance.
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h| 45
ARMv7 it is IMPDEF whether
> this bit is supported. And since ARMv7 mentions, that this bit is
> deprecated from the introduction of Virtualization Extensions
> I did not care to add this special case.
>
> On 12 Jun 2014, at 23:55, Greg Bellows greg.bell...@linaro.org>> wrote:
&
On 17 June 2014 02:41, Aggeler Fabian wrote:
>
> On 13 Jun 2014, at 20:27, Greg Bellows greg.bell...@linaro.org>> wrote:
>
>
>
>
> On 10 June 2014 18:54, Fabian Aggeler aggel...@ethz.ch>> wrote:
> Implements NSACR register with corresponding read/w
Hi Edgar,
I was just writing a test to verify the correct behavior of the SCR AW/FW
bits and I think there is an issue.
During an SCR write an initial valid mask is set from SCR_MASK which is
defined to not include these bits. Then these bits are hard-coded into the
write value using RES1. Last
Hi Peter,
Perhaps it is best to eliminate the made up "PL3" to avoid confusion with
EL3. Then this function can simply always return the correct level whether
it is PL or EL. Anywhere we require knowing whether we are secure or not
can be checked separately, which may be clearer anyhow. As well
thing that held me up from committing sooner was testing my changes.
Do you have a good approach for testing the changes?
Regards,
Greg
On 14 May 2014 03:58, Aggeler Fabian wrote:
> I see. What is Greg Bellows working on exactly? Also peripherals like
> TZASC, TZPC,...? My plan is to fo
On 13 May 2014 11:15, Fabian Aggeler wrote:
> From: Sergey Fedorov
>
> Define a new ARM CP register info list for the Security Extension feature.
> Register that list only for ARM cores with Security Extension support.
> Moving SCR into Security Extension register group.
>
> Signed-off-by: Serge
On 14 May 2014 00:53, Sergey Fedorov wrote:
> On 13.05.2014 20:15, Fabian Aggeler wrote:
> > arm_is_secure() function allows to determine CPU security state
> > if the CPU implements Security Extensions.
> >
> > Signed-off-by: Sergey Fedorov
> > Signed-off-by: Fabian Aggeler
> > ---
> > target
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