Conflict with Edgar's changes around the name of the security register
group v8_el3_cp_reginfo vs. security_cp_reginfo.
Given that there is a difference between the v7 regs and their v8
equivalents such as encoding, I propose we create 2 separate groups, but
map them to the same storage where applicable. This somewhat follows on
the SCR mapping discussion.
On 10 June 2014 18:54, Fabian Aggeler <aggel...@ethz.ch> wrote:
> Define a new ARM CP register info list for the ARMv7 Security Extension
> feature. Register that list only for ARM cores with Security Extension/EL3
> support. Moving Aarch32 SCR into Security Extension register group.
>
> Signed-off-by: Sergey Fedorov <s.fedo...@samsung.com>
> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
> ---
> target-arm/helper.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index e157cc2..d8d6637 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -792,9 +792,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> .access = PL1_RW, .writefn = vbar_write,
> .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
> .resetvalue = 0 },
> - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> - .resetvalue = 0, },
> { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
> .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> @@ -2216,6 +2213,13 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> +static const ARMCPRegInfo security_cp_reginfo[] = {
> + { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.scr_el3),
> + .resetvalue = 0, },
> + REGINFO_SENTINEL
> +};
> +
> static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -2479,6 +2483,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> }
> if (arm_feature(env, ARM_FEATURE_EL3)) {
> define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
> + define_arm_cp_regs(cpu, security_cp_reginfo);
> }
> if (arm_feature(env, ARM_FEATURE_MPU)) {
> /* These are the MPU registers prior to PMSAv6. Any new
> --
> 1.8.3.2
>
>
