On 9 June 2014 10:04, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Introduce new_el and new_mode in preparation for future patches
> that add support for taking exceptions to and from EL2 and 3.
> No functional change.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> target-arm/cpu.h | 7 +++++++
> target-arm/helper-a64.c | 24 +++++++++++++-----------
> target-arm/helper.c | 13 +++++++++++++
> 3 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 111577c..de00e01 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -461,6 +461,12 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr
> address, int rw,
> #define PSTATE_MODE_EL1t 4
> #define PSTATE_MODE_EL0t 0
>
> +/* Map EL and handler into a PSTATE_MODE. */
> +static inline unsigned int aarch64_pstate_mode(unsigned int el, bool
> handler)
> +{
> + return (el << 2) | handler;
> +}
> +
> /* Return the current PSTATE value. For the moment we don't support
> 32<->64 bit
> * interprocessing, so we don't attempt to sync with the cpsr state used
> by
> * the 32 bit decoder.
> @@ -709,6 +715,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env,
> int el)
> }
>
> void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
>
> /* Interface between CPU and Interrupt controller. */
> void armv7m_nvic_set_pending(void *opaque, int irq);
> diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
> index d647441..7d94a74 100644
> --- a/target-arm/helper-a64.c
> +++ b/target-arm/helper-a64.c
> @@ -443,10 +443,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> - target_ulong addr = env->cp15.vbar_el[1];
> + unsigned int new_el = arm_excp_target_el(cs, cs->exception_index);
> + target_ulong addr = env->cp15.vbar_el[new_el];
> + unsigned int new_mode = aarch64_pstate_mode(new_el, true);
> int i;
>
> - if (arm_current_pl(env) == 0) {
> + if (arm_current_pl(env) < new_el) {
> if (env->aarch64) {
> addr += 0x400;
> } else {
> @@ -464,14 +466,14 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
> env->exception.syndrome);
> }
>
> - env->cp15.esr_el[1] = env->exception.syndrome;
> - env->cp15.far_el[1] = env->exception.vaddress;
> + env->cp15.esr_el[new_el] = env->exception.syndrome;
> + env->cp15.far_el[new_el] = env->exception.vaddress;
>
> switch (cs->exception_index) {
> case EXCP_PREFETCH_ABORT:
> case EXCP_DATA_ABORT:
> qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
> - env->cp15.far_el[1]);
> + env->cp15.far_el[new_el]);
> break;
> case EXCP_BKPT:
> case EXCP_UDEF:
> @@ -488,15 +490,15 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
> }
>
> if (is_a64(env)) {
> - env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env);
> + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =
> pstate_read(env);
> aarch64_save_sp(env, arm_current_pl(env));
> - env->elr_el[1] = env->pc;
> + env->elr_el[new_el] = env->pc;
> } else {
> env->banked_spsr[0] = cpsr_read(env);
> if (!env->thumb) {
> - env->cp15.esr_el[1] |= 1 << 25;
> + env->cp15.esr_el[new_el] |= 1 << 25;
> }
> - env->elr_el[1] = env->regs[15];
> + env->elr_el[new_el] = env->regs[15];
>
> for (i = 0; i < 15; i++) {
> env->xregs[i] = env->regs[i];
> @@ -505,9 +507,9 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
> env->condexec_bits = 0;
> }
>
> - pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h);
> + pstate_write(env, PSTATE_DAIF | new_mode);
> env->aarch64 = 1;
> - aarch64_restore_sp(env, 1);
> + aarch64_restore_sp(env, new_el);
>
> env->pc = addr;
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 17cf80e..86e098f 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3217,6 +3217,11 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env,
> uint32_t mode)
> return 0;
> }
>
> +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
> +{
> + return 1;
> +}
> +
> #else
>
> /* Map CPU modes onto saved register banks. */
> @@ -3272,6 +3277,14 @@ void switch_mode(CPUARMState *env, int mode)
> env->spsr = env->banked_spsr[i];
> }
>
> +/*
> + * Determine the target EL for a given exception type.
> + */
> +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
> +{
> + return 1;
> +}
> +
>
Unless this is just a preparation to make the non CONFIG_USER_ONLY version
of this different, this can be moved out of the ifdef and made common.
> static void v7m_push(CPUARMState *env, uint32_t val)
> {
> CPUState *cs = CPU(arm_env_get_cpu(env));
> --
> 1.8.3.2
>
>
Otherwise...
Reviewed-by: Greg Bellows <greg.bell...@linaro.org>
