From: Rob Herring
Enable the generic PCI host on ARM virt platform.
TODO:
The memory regions aliases are hard coded in the host ATM. These probably
need to become QOM properties.
Signed-off-by: Rob Herring
---
hw/arm/virt.c | 57 +
1
From: Rob Herring
Add a generic PCI host controller for virtual platforms. This is for ARM
virtual platforms at the moment, but has nothing ARM specific. This
matches the generic PCI host driver added in the 3.16 kernel.
Functioning with OHCI (usb disk), but not LSI SCSI which doesn't f
On Wed, May 14, 2014 at 12:51 PM, Peter Maydell
wrote:
> On 5 May 2014 17:00, Rob Herring wrote:
>> From: Rob Herring
>>
>> Now that we have PSCI emulation, enable it for the virt platform.
>> This simplifies the virt machine a bit now that PSCI and SMP no longer
>
From: Rob Herring
The AArch64 kermel Image format defines the load offset in its header.
Retrieve the offset from the file instead of hardcoding it to 0x8.
Use of the hardcoded value will break when text_offset randomization is
added to the kernel.
Signed-off-by: Rob Herring
---
hw/arm
On Wed, May 14, 2014 at 12:44 PM, Peter Maydell
wrote:
> On 5 May 2014 17:00, Rob Herring wrote:
>> From: Rob Herring
>>
>> Add the infrastructure to handle and emulate hvc and smc exceptions.
>> This will enable emulation of things such as PSCI calls. This co
On Wed, May 14, 2014 at 4:25 PM, Peter Maydell wrote:
> On 14 May 2014 20:15, Rob Herring wrote:
>> On Wed, May 14, 2014 at 12:51 PM, Peter Maydell
>> wrote:
>>> My suggestion to Pranav was that we abstract away the "which PSCI
>>> version?" decision i
On Wed, May 14, 2014 at 1:12 PM, Peter Maydell wrote:
> On 5 May 2014 17:00, Rob Herring wrote:
>> From: Rob Herring
>>
>> Add support for handling PSCI calls in system emulation. Both version
>> 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
From: Rob Herring
Signed-off-by: Rob Herring
---
Mark, I guessing you don't want to stay as maintainer?
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 97c9fa1..5ad7dcc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -
On Thu, May 22, 2014 at 6:18 AM, Pranavkumar Sawargaonkar
wrote:
> If we have PSCI v0.2 emulation available for KVM ARM/ARM64 or TCG then
> we need to provide PSCI v0.2 compatible string via generated DTB.
>
> Signed-off-by: Pranavkumar Sawargaonkar
> Signed-off-by: Anup Patel
R
From: Rob Herring
This series adds support for emulating ARM PSCI calls. PSCI or Power
State Coordination Interface is an ARM standard for controlling cpu
power states. This series supports both AArch32 and AArch64 using HVC or
SMC calls.
This is based on version 6 of Pranavkumar Sawargaonkar&#
From: Rob Herring
In preparation to add system mode only calls to
aarch64_cpu_do_interrupt, compile it for system mode only and don't set
the do_interrupt callback for user mode emulation. User mode emulation
should never get interrupts and thus should not have a exception handler
functio
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI and SMP no longer
need to be KVM only features.
Signed-off-by: Rob Herring
---
v2:
- Rebased. Mostly a whitespace change removing the kvm_enabled() check
From: Rob Herring
Enable PSCI emulation on highbank and midway platforms.
Note that this requires fixing the PSCI function IDs in the DTB to match
what QEMU is using. This should get fixed.
Signed-off-by: Rob Herring
---
v2:
- Add error_abort on setting of start-powered-off.
hw/arm
From: Rob Herring
Add support for handling PSCI calls in system emulation. Both version
0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
by setting "psci-method" QOM property on the cpus to SMC or HVC
emulation and having PSCI binding in their dtb.
Signed-o
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
---
v2:
- add syn_aa32_smc
- add missing
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emulation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
---
v2:
- Add vmstate for powered_off
target-arm/cpu-qom.h | 2 ++
target-arm
on=pl011,0x... command line arguments.
>
> Signed-off-by: Ard Biesheuvel
I have this same patch in my tree. BTW, you do still need just
"earlycon" on the command-line to get an early console.
Reviewed-by: Rob Herring
Rob
> ---
> hw/arm/virt.c | 2 ++
> 1 file changed, 2
gt;> after not :).
>>
>> Hi Alex,
>>
>> Unfortunately I think the last one was this week. If you are available
>> next week I would propose to setup a short call next week.
>
>
> Sure!
>
>
>> Who are the
>> required people in the call aside us and Peter?
>
>
> It would be good if we could have one person on the call who has a very good
> understanding of cross-platform device trees. Scott Wood or Rob Herring come
> to my mind here.
>
> Scott, Rob, would either of you be available for a quick call on device tree
> abstraction levels in QEMU Tuesday next week?
Yes, I can.
Rob
Mark,
On 12/22/2011 12:20 PM, Mark Langsdorf wrote:
> From: Rob Herring
>
> Signed-off-by: Rob Herring
> Signed-off-by: Mark Langsdorf
> ---
> hw/a9mpcore.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore
On 01/05/2012 08:35 AM, Mark Langsdorf wrote:
> On 01/05/2012 08:26 AM, Alexander Graf wrote:
>>
>> On 05.01.2012, at 15:16, Andreas Färber wrote:
>>
>>> Am 05.01.2012 14:52, schrieb Mark Langsdorf:
>>>> From: Rob Herring
>>>>
>>>
On 01/05/2012 09:32 AM, Peter Maydell wrote:
> On 5 January 2012 15:11, Rob Herring wrote:
>> Mark, there is not a qemu code dependency on Trustzone support, so we
>> don't need to wait for that to add highbank support.
>
> That's good, because Trustzone support
On 01/06/2012 12:37 PM, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>
> Hello, Mark. According to technical specification on Calxeda website,
> highbank SoC has SD 3.0 host controller, are you planning to implement
> it in qemu? I'm asking because I recently have submitte
On 01/19/2012 03:44 PM, Peter Maydell wrote:
> On 19 January 2012 21:31, Mark Langsdorf wrote:
>> +highbank_binfo.board_id = 0xEC10100f; /* provided by deviceTree */
>
> Where does this number come from? It's not in
> http://www.arm.linux.org.uk/developer/machines/
>
> Is 3027 (==0xbd3) you?
On 01/20/2012 02:47 AM, Peter Maydell wrote:
> On 19 January 2012 23:17, Rob Herring wrote:
>> On 01/19/2012 03:44 PM, Peter Maydell wrote:
>>> On 19 January 2012 21:31, Mark Langsdorf wrote:
>>>> +highbank_binfo.board_id = 0xEC10100f; /* provided by deviceT
From: Rob Herring
ARMv8 has both AArch32 and AArch64 versions of ID registers. Both sets
of registers are accessible in AArch64 state, but only . Update the
definitions to allow AArch64 access.
This fixes booting on recent (linux-next for 3.15) linux kernels which
add access to ID_ISAR5
On Thu, Mar 6, 2014 at 1:33 PM, Peter Maydell wrote:
> Add Cortex-A57 processor.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/cpu64.c | 43 +++
> 1 file changed, 43 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index d4fb1
en we could just say "-cpu host only makes sense for
> the virt machine", but we're not there right now.)
>
> Peter Maydell (2):
> hw/arm/highbank: Don't segfault on unknown CPU names
> hw/arm/vexpress, hw/arm/highbank: Don't insist that CPU has reset-cbar
> property
For both:
Reviewed-by: Rob Herring
On Thu, Apr 10, 2014 at 10:02 AM, Peter Maydell
wrote:
> On 17 March 2014 07:12, Peter Crosthwaite
> wrote:
>> On Fri, Mar 7, 2014 at 5:33 AM, Peter Maydell
>> wrote:
>>> Support the Cortex-A57 in the virt machine model.
>>>
>>> Signed-off-by: Peter Maydell
>>> ---
>>> This should perhaps not
On Tue, Feb 11, 2014 at 5:29 PM, Peter Maydell wrote:
> On 11 February 2014 23:19, Rob Herring wrote:
>> From: Rob Herring
>>
>> Several platforms make smc calls for things such as PL310 cache setup.
>> In these cases, making smc a nop rather than an illegal instr
we split out the CPU and
> private memory region init to its own function.
>
> Signed-off-by: Peter Maydell
> Reported-by: Rob Herring
> ---
> Thanks to Rob for tracking down this SMP boot issue and identifying
> the offending kernel change (which personally I think is a terrible
From: Rob Herring
MPIDR register is a machine configurable option and current kernels require
the value to match with DT cpu reg properties. So add a property for MPIDR
value and allow platforms to override.
ARM_FEATURE_MPIDR is not used here because it is set too late.
Signed-off-by: Rob
From: Rob Herring
Calxeda highbank platform uses a cluster id of 9 which makes MPIDR
register be 0x890n where n is the core number. This causes problems
on current kernels expecting the MPIDR to match DT cpu reg property.
Midway is "normal" and has a cluster id of 0, so it doe
On Mon, Feb 24, 2014 at 4:28 PM, Peter Maydell wrote:
> On 24 February 2014 22:14, Rob Herring wrote:
>> From: Rob Herring
>> MPIDR register is a machine configurable option and current kernels require
>> the value to match with DT cpu reg properties. So add a property f
things getting
> worse on your test case with this patch if you have the GIC
> fix applied too?
No, At least with the mptimers, it improves things reducing the sched
delay messages.
Tested-by: Rob Herring
>
> include/exec/cpu-defs.h | 1 +
> target-arm/helper.h | 1 +
> target
On Wed, Feb 26, 2014 at 4:31 AM, Peter Maydell wrote:
> On 26 February 2014 03:32, Hu Tao wrote:
>> On Wed, Feb 26, 2014 at 10:49:59AM +0800, Hu Tao wrote:
>>> On Sat, Feb 15, 2014 at 04:07:24PM +, Peter Maydell wrote:
>>> > From: Rob Herring
>
>>>
From: Rob Herring
Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re
From: Rob Herring
Offset 4 is UARTRSR/UARTECR, not the UARTCR. As framing and parity errors
will never occur, we can ignore writes to this register.
Signed-off-by: Rob Herring
---
hw/char/pl011.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char
On Fri, Feb 28, 2014 at 4:41 AM, Peter Maydell wrote:
> On 28 February 2014 01:37, Rob Herring wrote:
>> From: Rob Herring
>>
>> Offset 4 is UARTRSR/UARTECR, not the UARTCR. As framing and parity errors
>> will never occur, we can ignore writes to this register.
>
On 31 January 2014 09:45, Peter Maydell wrote:
> The raw read and write functions were using the ARM_CP_64BIT flag in
> ri->type to determine whether to treat the register's state field as
> uint32_t or uint64_t; however AArch64 register info structs don't use
> that flag. Abstract out the "how bi
I've bisected a problem with system emulation and SMP kernels using
per cpu timers to this commit. I can reproduce this problem on ARM
emulation with both ARM generic timers (only in 1.7.0) and ARM MPCore
timers. Using a single broadcast timer in the guest kernel works fine.
My host is ubuntu 13.1
On Sat, Feb 8, 2014 at 9:20 AM, Alex Bligh wrote:
> Paolo,
>
> On 8 Feb 2014, at 13:26, Paolo Bonzini wrote:
>
>>>
>>> What I'd suggest you do is run qemu within gdb, and when you have
>>> seen the sluggish behaviour, set a breakpoint in timerlist_run_timers
>>> just before the line saying cb(opaq
From: Rob Herring
Non-PCI AHCI support is broken due to assertion failures when trying
to convert AHCIState to a PCIDevice pointer as AHCIState can have
different container structs. Fix this by using the non-asserting object
cast and checking the returned pointer is not NULL.
The AddressSpace
From: Rob Herring
Several platforms make smc calls for things such as PL310 cache setup.
In these cases, making smc a nop rather than an illegal instruction
is sufficient for qemu to work.
Signed-off-by: Rob Herring
---
target-arm/translate.c | 20 +++-
1 file changed, 11
From: Rob Herring
Like was done for AArch32 for WFE, implement both WFE and YIELD as a
yield operation. This speeds up multi-core system emulation.
Signed-off-by: Rob Herring
---
target-arm/translate-a64.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/translate-a64.c b
On Thu, Apr 17, 2014 at 5:02 AM, Peter Maydell wrote:
> On 2 April 2014 13:47, Peter Maydell wrote:
>> On 2 April 2014 13:11, Peter Crosthwaite
>> wrote:
>>> Like others, I have been carrying this change locally. Good to see it up!
>>
>> Why are you all booting raw Images anyway (just out of cu
On Wed, Apr 16, 2014 at 2:14 PM, Nicolas Pitre wrote:
> On Wed, 16 Apr 2014, Christopher Covington wrote:
>
>> On 04/15/2014 06:44 AM, Daniel Thompson wrote:
>> > Hi Folks
[snip]
>> Or could we patch up the linker script to set zero-based ELF load
>> memory addresses (LMAs) [4] so that the physi
On Thu, Apr 17, 2014 at 3:16 PM, Russell King - ARM Linux
wrote:
> On Thu, Apr 17, 2014 at 04:06:16PM -0400, Nicolas Pitre wrote:
>> On Thu, 17 Apr 2014, Rob Herring wrote:
>> > Better yet, we should adopt the arm64 Image header which has this and
>> > other fields
On Thu, Apr 17, 2014 at 4:35 PM, Russell King - ARM Linux
wrote:
> On Thu, Apr 17, 2014 at 04:18:45PM -0500, Rob Herring wrote:
>> The problem here is more than just the TEXT_OFFSET changed. From what
>> I've heard, there are some QC chips which need much more reserved
On Thu, Apr 24, 2014 at 12:54 PM, Peter Maydell
wrote:
> For an AArch64 CPU which supports 64K pages, having the GIC
> register banks at 4K offsets is potentially awkward. Move
> them out to being at 64K offsets. (This is harmless for
> AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is sim
On Thu, Apr 10, 2014 at 6:46 AM, Pranavkumar Sawargaonkar
wrote:
> If we have in-kernel emulation of PSCI v0.2 for KVM ARM/ARM64 then
> we enable PSCI v0.2 for each VCPU at the time of VCPU init hence we
> need to provide PSCI v0.2 function IDs via generated DTB.
>
> This patch updates generated D
On Thu, Apr 10, 2014 at 6:46 AM, Pranavkumar Sawargaonkar
wrote:
> Provide QEMU PSCI v0.2 constants for non-KVM code; this will
> allow us to avoid an #ifdef in boards which set up a PSCI v0.2
> node in the device tree.
>
> Signed-off-by: Pranavkumar Sawargaonkar
> Signed-off-by: Anup Patel
> --
On Mon, May 5, 2014 at 6:42 AM, Pranavkumar Sawargaonkar
wrote:
> Hi Peter,
>
> On 5 May 2014 16:14, Peter Maydell wrote:
>> On 5 May 2014 10:00, Pranavkumar Sawargaonkar wrote:
>>> Introduce a common kvm_arm_vcpu_init() for doing KVM_ARM_VCPU_INIT
>>> ioctl in KVM ARM and KVM ARM64. This also h
On Mon, May 5, 2014 at 3:57 AM, Pranavkumar Sawargaonkar
wrote:
> If we have in-kernel emulation of PSCI v0.2 for KVM ARM/ARM64 then
> we enable PSCI v0.2 for each VCPU at the time of VCPU init hence we
> need to provide PSCI v0.2 compatible string via generated DTB.
>
> This patch updates generat
On Mon, May 5, 2014 at 9:06 AM, Rob Herring wrote:
> On Mon, May 5, 2014 at 3:57 AM, Pranavkumar Sawargaonkar
> wrote:
>> If we have in-kernel emulation of PSCI v0.2 for KVM ARM/ARM64 then
>> we enable PSCI v0.2 for each VCPU at the time of VCPU init hence we
>> n
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 7 ++-
2 files changed
From: Rob Herring
This series adds support for enulating ARM PSCI calls. PSCI or Power
State Coordination Interface is an ARM standard for controlling cpu
power states. This series supports both AArch32 and AArch64 using HVC or
SMC calls.
This series is based on Pranavkumar Sawargaonkar&#
From: Rob Herring
User mode emulation should never get interrupts and thus should not
use the system emulation exception handler function.
Signed-off-by: Rob Herring
---
target-arm/cpu64.c | 4
target-arm/helper-a64.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/target
From: Rob Herring
Enable PSCI enulation on highbank and midway platforms.
Note that this requires fixing the PSCI function IDs in the DTB to match
what QEMU is using. This should get fixed.
Signed-off-by: Rob Herring
---
hw/arm/highbank.c | 8
1 file changed, 8 insertions(+)
diff
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
---
target-arm/cpu-qom.h | 3
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI and SMP no longer
need to be KVM only features.
Signed-off-by: Rob Herring
---
Note: This will need to be rebased as comments on KVM PSCI 0.2 support
are
From: Rob Herring
Add AArch64 support to arm_cpu_set_pc and make it available to other files.
Signed-off-by: Rob Herring
---
target-arm/cpu.c | 7 ---
target-arm/cpu.h | 12
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
From: Rob Herring
Add support for handling PSCI calls in system emulation. Both version
0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
by setting "psci-method" QOM property on the cpus to SMC or HVC
emulation and having PSCI binding in their dtb.
Signed-o
On Tue, May 6, 2014 at 12:24 AM, Pranavkumar Sawargaonkar
wrote:
> Hi Rob, Peter,
>
> On 5 May 2014 20:13, Peter Maydell wrote:
>> On 5 May 2014 15:09, Rob Herring wrote:
>>> On Mon, May 5, 2014 at 9:06 AM, Rob Herring wrote:
>>>> This does not compile for m
On Sun, Mar 2, 2014 at 2:20 PM, Peter Maydell wrote:
> On 28 February 2014 00:57, Rob Herring wrote:
>> From: Rob Herring
>>
>> Intermittent issues have been seen where no serial input occurs. It
>> appears the pl011 gets in a state where the rx interrupt never fires
t;> >> +++ b/hw/arm/virt.c
>> >> @@ -187,11 +187,26 @@ static void create_fdt(VirtBoardInfo *vbi)
>> >> qemu_fdt_add_subnode(fdt, "/psci");
>> >> qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci&qu
From: Rob Herring
Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re
From: Rob Herring
The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.
Signed-off-by: Rob Herring
---
hw/char/pl011.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/char/pl011.c b/hw/char
From: Rob Herring
When setting the fifo trigger level, the rx interrupt needs to be asserted
if the current fifo level matches. This is more for correctness as the
level is currently never changed.
Signed-off-by: Rob Herring
---
hw/char/pl011.c | 4
1 file changed, 4 insertions(+)
diff
From: Rob Herring
Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re
From: Rob Herring
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
On Sun, Mar 16, 2014 at 11:44 AM, Peter Maydell
wrote:
> On 16 March 2014 15:57, Peter Maydell wrote:
>> On 14 March 2014 18:22, Rob Herring wrote:
>>> From: Rob Herring
>>>
>>> When setting the fifo trigger level, the rx interrupt needs to be asserted
&
On Mon, Feb 10, 2014 at 6:32 PM, Peter Maydell wrote:
> On 10 February 2014 23:02, Rob Herring wrote:
>> From: Rob Herring
>>
>> Non-PCI AHCI support is broken due to assertion failures when trying
>> to convert AHCIState to a PCIDevice pointer as AHCIState can
From: Rob Herring
Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re
From: Rob Herring
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
From: Rob Herring
Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re
From: Rob Herring
The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.
Signed-off-by: Rob Herring
Reviewed-by: Peter Maydell
---
hw/char/pl011.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
On Mon, Jun 2, 2014 at 11:16 AM, Claudio Fontana wrote:
> Hello Peter,
>
> I am porting OSv to AArch64, and I have some working code running on
> the Foundation Models,
> where I run qemu natively with --enable-kvm,
>
> which does not seem to work when run instead on top of the system emulation.
>
On Tue, Jun 3, 2014 at 6:14 AM, Peter Maydell wrote:
> On 23 May 2014 03:30, Rob Herring wrote:
>> From: Rob Herring
>>
>> Add support for handling PSCI calls in system emulation. Both version
>> 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
nop them.
> Use the ARM boot board-setup feature to implement this.
>
> Signed-off-by: Peter Crosthwaite
Thanks for doing this. I'm not a big fan of how the machine code for
boot code is embedded into C in qemu, but that's a separate issue.
Acked-by: Rob Herring
> ---
On Tue, Oct 27, 2015 at 4:30 PM, Peter Crosthwaite
wrote:
>
>
> On Tue, Oct 27, 2015 at 1:29 PM, Rob Herring wrote:
>>
>> On Sun, Oct 25, 2015 at 6:13 PM, Peter Crosthwaite
>> wrote:
>> > Firstly, enable monitor mode and PSCI, both are which are featu
On Mon, Feb 1, 2016 at 7:51 AM, Eric Auger wrote:
> This function returns the host device tree blob from sysfs
> (/proc/device-tree). It uses a recursive function inspired
> from dtc read_fstree.
>
> Signed-off-by: Eric Auger
>
> ---
> v5 -> v6:
> - fix some spelling mistakes
> - error_report + e
On Mon, Feb 1, 2016 at 10:22 AM, Eric Auger wrote:
> Hi Rob,
> On 02/01/2016 05:15 PM, Rob Herring wrote:
>> On Mon, Feb 1, 2016 at 7:51 AM, Eric Auger wrote:
>>> This function returns the host device tree blob from sysfs
>>> (/proc/device-tree). It uses a recurs
On Fri, Nov 13, 2015 at 10:03:55PM -0500, Gabriel L. Somlo wrote:
> From: Gabriel Somlo
>
> Remove redundant details from
> Documentation/devicetree/bindings/arm/fw-cfg.txt,
> and replace them with a pointer to the more comprehensive
> fw_cfg documentation privided by
> Documentation/ABI/testing/
On Mon, Nov 16, 2015 at 2:38 AM, Paolo Bonzini wrote:
>
>
> On 15/11/2015 03:07, Rob Herring wrote:
>> We generally don't want DT docs to depend on other kernel documentation.
>
> DT docs do not contain a copy of the data sheets, either. There is no
> reason to s
e QEMU source tree.
>
> Signed-off-by: Gabriel Somlo
> Cc: Laszlo Ersek
Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/arm/fw-cfg.txt | 38
> ++--
> 1 file changed, 2 insertions(+), 36 deletions(-)
>
> diff --git a/Documentation/devicetr
On Fri, Jul 11, 2014 at 4:28 AM, Alvise Rigo
wrote:
> The kernel version is a very recent one: v3.16.0-rc1.
> Maybe you are right. I will test some older version to see if I'm able
> to reproduce the issue.
BTW, the lsi driver has compile time option to use i/o or memory
accesses. I usually test
On Tue, Sep 27, 2022 at 6:25 AM Peter Maydell wrote:
>
> On Tue, 27 Sept 2022 at 11:12, Jean-Philippe Brucker
> wrote:
> >
> > Since the pl061 device can be used as interrupt controller, its node
> > should contain "interrupt-controller" and "#interrupt-cells" properties.
>
> It *can* be, but thi
scon-poweroff']} should not be valid
> >> under {'type': 'object'}
> >>From schema:
> >> /home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
> >> /stuff/qemu/qemu.dtb: soc: reboot: {'value':
On Wed, Nov 27, 2019 at 09:42:50AM +0100, Geert Uytterhoeven wrote:
> Add Device Tree bindings for a GPIO repeater, with optional translation
> of physical signal properties. This is useful for describing explicitly
> the presence of e.g. an inverter on a GPIO line, and was inspired by the
> non-Y
On Fri, Dec 6, 2019 at 3:17 AM Geert Uytterhoeven wrote:
>
> Hi Rob,
>
> On Thu, Dec 5, 2019 at 10:06 PM Rob Herring wrote:
> > On Wed, Nov 27, 2019 at 09:42:50AM +0100, Geert Uytterhoeven wrote:
> > > Add Device Tree bindings for a GPIO repeater, with optional tr
On Thu, May 5, 2022 at 6:41 AM Leif Lindholm wrote:
>
> The sbsa-ref machine is continuously evolving. Some of the changes we
> want to make in the near future, to align with real components (e.g.
> the GIC-700), will break compatibility for existing firmware.
>
> Introduce two new properties to t
On Tue, May 17, 2022 at 11:50 AM Peter Maydell wrote:
>
> On Tue, 17 May 2022 at 14:27, Rob Herring wrote:
> >
> > On Thu, May 5, 2022 at 6:41 AM Leif Lindholm
> > wrote:
> > >
> > > The sbsa-ref machine is continuously evolving. Some of the changes we
On Tue, Sep 27, 2022 at 6:28 AM Peter Maydell wrote:
>
> On Tue, 27 Sept 2022 at 11:12, Jean-Philippe Brucker
> wrote:
> >
> > The devicetree specification requires that nodes use a generic name
> > where appropriate. Fix the corresponding dt-validate warnings:
>
> Either:
> (1) guests are lookin
On Tue, Sep 27, 2022 at 6:56 AM Peter Maydell wrote:
>
> On Tue, 27 Sept 2022 at 11:12, Jean-Philippe Brucker
> wrote:
> > The node name of the gpio-key devicetree node should be "key-poweroff":
> >
> > gpio-keys: 'poweroff' does not match any of the regexes:
> > '^(button|event|key|switch|(bu
I'm running current master of QEMU using virgl and display backend
"gtk,gl=on". I get no guest mouse events unless I force CONFIG_GTK_GL
off or make the following patch. Key events work fine. I'm on ubuntu
16.04 with GTK 3.18 (ubuntu 15.10/GTK 3.16 also had the same issue).
I've had this problem fo
On Thu, Jan 2, 2025 at 8:57 AM Alireza Sanaee wrote:
>
> On Wed, 25 Dec 2024 11:03:42 +0800
> Zhao Liu wrote:
>
> > > > About smp-cache
> > > > ===
> > > >
> > > > The API design has been discussed heavily in [3].
> > > >
> > > > Now, smp-cache is implemented as a array integrated in
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