On Tue, Oct 27, 2015 at 4:30 PM, Peter Crosthwaite <crosthwaitepe...@gmail.com> wrote: > > > On Tue, Oct 27, 2015 at 1:29 PM, Rob Herring <r...@kernel.org> wrote: >> >> On Sun, Oct 25, 2015 at 6:13 PM, Peter Crosthwaite >> <crosthwaitepe...@gmail.com> wrote: >> > Firstly, enable monitor mode and PSCI, both are which are features of >> > this board. >> > >> > In addition to PSCI, this board also uses SMC for cache maintainence >> > ops. This means we need a secure monitor to catch these and nop them. >> > Use the ARM boot board-setup feature to implement this. >> > >> > Signed-off-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com> >> >> Thanks for doing this. I'm not a big fan of how the machine code for >> boot code is embedded into C in qemu, but that's a separate issue. >> >> Acked-by: Rob Herring <r...@kernel.org> >> > > Thanks, > > One question while you are here if you have the answer off-hand. Does the > highbank firmware switch out of secure mode before booting the kernel or > stay in secure mode? I know of platforms that regularly boot Linux into > secure mode, so if it is one of those we might as well get it right > per-board when doing Peters proposed idea.
The firmware switches out of secure mode. The kernel doesn't allow switching, so it is true of all platforms that run non-secure (although some do it in u-boot). Rob
