[PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

"5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c| 3 +- target/riscv/cpu.h| 8 ++ target/r

[PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..041f0b3e2e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1522,7 +1522,7 @@ static RISCVException

[PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support

VS-mode by the Hypervisor. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf [1]: https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/riscv_irq_filter [2]: https://github.com/rajnesh-kanwal/opensbi/tre

[PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 21 - 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..de55bfb775 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

ts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanw

[PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local interrupt as well. This change adds a check for async flag before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target

[PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled

: Rajnesh Kanwal --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..90460cfe64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1288,6 +1288,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error

Re: [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

> > On Thu, May 18, 2023 at 1:39 PM Rajnesh Kanwal wrote: >> >> RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local >> interrupt as well. This change adds a check for async flag >> before invoking semihosting logic. >> >> Signed-off-by: Ra

[PATCH v2 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..041f0b3e2e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1522,7 +1522,7 @@ static RISCVException

[PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu_helper.c | 10 -- 1 file

[PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled

: Rajnesh Kanwal --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..269a094f42 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1280,6 +1280,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error

[PATCH v2 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

"5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c| 3 +- target/riscv/cpu.h| 8 ++ target/r

[PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

VS-mode by the Hypervisor. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter [2]: https://github.com/rajnesh-kanwal/linux/co

[PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 ++--- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..de55bfb775 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v2 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

ts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanw

Re: [PATCH 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

On Mon, May 22, 2023 at 6:18 PM Daniel Henrique Barboza wrote: > > > > On 5/18/23 08:38, Rajnesh Kanwal wrote: > > This change adds support for inserting virtual interrupts from HS-mode > > into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering > &

[PATCH 4/6] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal

[PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++ target/riscv/insn32.decode | 1

[PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 159 + 3 files changed, 166 insertions

[PATCH 2/6] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu_bits.h | 154 1 file changed, 154 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 86e15381c8..71ddccaf1a 100644 --- a/target

[PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

e CTR Ext. The Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream The opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream The Linux kernel patches can be found here: https://github.com/rajnesh-kanwal/linux/tree/ctr_upstr

[PATCH 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 4 ++ target

[PATCH 1/6] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f22df04cfd..9cb1a1b4ec 100644 --- a/target

[PATCH 0/2] Minor fixes and improvements for Virtual IRQs

confusion and any future issues. Patches can be found here on github: https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/irq_fixes Signed-off-by: Rajnesh Kanwal --- Rajnesh Kanwal (2): target/riscv: Extend virtual irq csrs masks to be 64 bit wide. target/riscv: Move Guest irqs out o

[PATCH 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-of

[PATCH 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.

t and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal --- target/riscv/csr.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c

[PATCH v2 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.

t and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/csr.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deleti

[PATCH v2 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-of

[PATCH v2 0/2] target/riscv: Minor fixes and improvements for Virtual IRQs

confusion and any future issues. Patches can be found here on github [0] and v1 of the series can be found here [1]. Patches are based on alistair/riscv-to-apply.next. [0] https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/irq_fixes_v2 [1] https://lore.kernel.org/all/20240513114602.72

Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Thanks Jason for your review. On Tue, Jun 4, 2024 at 11:14 AM Jason Chien wrote: > > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and > sctrdepth CSRs handling. > > Signed-off-by: Rajnesh Kanwal > --- >

[PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu_bits.h | 154 1 file changed, 154 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 86e15381c8..71ddccaf1a 100644 --- a/target

[PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f22df04cfd

[PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.

Ext. The Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream_v2 The opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 The Linux kernel patches can be found here: https://github.com/rajnesh-kanwal/linux/tree/ctr_

[PATCH v2 4/6] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal

[PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 4

[PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 7 target/riscv/helper.h | 1

[PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 128 + 3 files changed, 135 insertions

Re: [PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

ll patches are acked: > > https://lore.kernel.org/qemu-riscv/20230526162308.22892-1-rkan...@rivosinc.com/ > > > It'll probably conflict with current Alistair's riscv-to-apply.next though, so > perhaps Rajnesh could gather the acks and send a rebased version. > > > Thanks

[PATCH v3 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 85a31dc420..0241c77719 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1524,7 +1524,7

[PATCH v3 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled

: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2b94b6a6..0e7620d1ad 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1492,7 +1492,12 @@ static void

[PATCH v3 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

r. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter [2]: https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_fil

[PATCH v3 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

ts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanw

[PATCH v3 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 ++--- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef9cf21c0c..7092aeb7f0 100644 --- a

[PATCH v3 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

"5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c| 3 +- tar

[PATCH v3 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c

[PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b4ab56c40..d99d954ff3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1525,7 +1525,7

[PATCH v4 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

r. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter [2]: https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_fil

[PATCH v4 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 ++--- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8ffa5ee38..6fe32e6b38 100644 --- a

[PATCH v4 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

ts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanw

[PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled

: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a28918ab30..34e034b9f3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg

[PATCH v4 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

"5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c| 3 +- tar

[PATCH v4 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c

[PATCH v5 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c

[PATCH v5 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

r. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter [2]: https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_filter [3]: htt

[PATCH v5 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

ts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf Signed-off-by: Rajnesh Kanwal Revi

[PATCH v5 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled

: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 418b040d6d..bbce254ee1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg

[PATCH v5 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 ++--- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8ffa5ee38..6fe32e6b38 100644 --- a

[PATCH v5 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

"5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c| 3 +- target/riscv/cpu

[PATCH v5 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 30cc21e979..4847b47a98 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1525,7 +1525,7

Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.

2020 at 13:51, wrote: > > > > From: Rajnesh Kanwal > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > interrupt and VS mode interrupts are being shifted to represent > > S mode interrupts in this function. So when the cause returned by >

Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.

ronous exception values must be decremented. So, > checking if this is an async exception should do the job. > > Jose > > On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal > wrote: > > > > Hello Jose, > > > > Sorry I didn't see that as it hadn't became a part

Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.

already submitted almost this exact patch a few weeks ago. > > To QEMU? I don't see the patch. > > Alistair > > > > > Jose > > > > On Sun, 23 Feb 2020 at 13:51, wrote: > > > > > > From: Rajnesh Kanwal > > > > > > Curr

Re: [PATCH v2 4/6] target/riscv: Add support to record CTR entries.

Hi Jason, On Wed, Jun 26, 2024 at 4:49 AM Jason Chien wrote: > > Hi Rajnesh, > > On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: > > This commit adds logic to records CTR entries of different types > > and adds required hooks in TCG and interrupt/Exception logic to > &g

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

On Tue, Aug 27, 2024 at 10:28 AM Frank Chang wrote: > > Rajnesh Kanwal 於 2024年6月19日 週三 下午11:27寫道： > > > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and > > sctrdepth CSRs handling. > > > > Signed-off-by: Rajnesh Kanwal > > --- > &

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

On Thu, Oct 17, 2024 at 4:05 PM Frank Chang wrote: > > On Thu, Oct 17, 2024 at 7:18 PM Rajnesh Kanwal wrote: >> >> On Tue, Aug 27, 2024 at 10:28 AM Frank Chang wrote: >> > >> > Rajnesh Kanwal 於 2024年6月19日 週三 下午11:27寫道： >> > > >> > >

[PATCH v3 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 144 + 3 files changed, 151

[PATCH v3 2/6] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5 Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu_bits.h | 94 + 1 file changed, 94 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext.

re is the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v3 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux k

[PATCH v3 4/6] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal

[PATCH v3 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 26

[PATCH v3 1/6] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Jason Chien --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v3 5/6] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++ target/riscv/helper.h | 1

[PATCH v4 1/7] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Jason Chien --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v4 2/7] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5 Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu_bits.h | 94 + 1 file changed, 94 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v4 3/7] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 144 + 3 files changed, 151

[PATCH v4 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 26

[PATCH v4 7/7] target/riscv: machine: Add Control Transfer Record state description

Add a subsection to machine.c to migrate CTR CSR state Signed-off-by: Rajnesh Kanwal --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index e1bdc31c7c53a8a4f539113d501c8e46f7a914e9

Re: [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext.

On Tue, Nov 5, 2024 at 3:58 PM Richard Henderson wrote: > > On 11/4/24 21:51, Rajnesh Kanwal wrote: > > target/riscv/cpu.c | 26 ++- > > target/riscv/cpu.h | 13 ++ > > target/riscv/cpu_bits.h

[PATCH v4 0/7] target/riscv: Add support for Control Transfer Records Ext.

re is the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v4 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux k

[PATCH v4 5/7] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++ target/riscv/helper.h | 1

[PATCH v4 4/7] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal

Re: [PATCH v5 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

On Mon, Feb 3, 2025 at 2:58 AM Alistair Francis wrote: > > On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote: > > > > CTR entries are accessed using ctrsource, ctrtarget and ctrdata > > registers using smcsrind/sscsrind extension. This commits extends > > the c

[PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++ target/riscv/helper.h

[PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Jason Chien --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v6 6/7] target/riscv: machine: Add Control Transfer Record state description

Add a subsection to machine.c to migrate CTR CSR state Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index

[PATCH v6 7/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv

[PATCH v6 2/7] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5 Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu_bits.h | 145 1 file changed, 145 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

s the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux k

[PATCH v6 3/7] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 144

[PATCH v6 4/7] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal Acked

Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis wrote: > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote: > > > > This series enables Control Transfer Records extension support on riscv > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. &g

[PATCH v7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- This series

Re: [PATCH v4 4/7] target/riscv: Add support to record CTR entries.

Thanks Richard. I have incorporated your feedback in v5. -Rajnesh On Wed, Dec 4, 2024 at 7:30 PM Richard Henderson wrote: > > On 12/4/24 06:56, Rajnesh Kanwal wrote: > > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc > > b/target/riscv/insn_trans/trans_privileg

[PATCH v5 5/7] target/riscv: Add CTR sctrclr instruction.

CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++ target/riscv/helper.h | 1

[PATCH v5 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 26

[PATCH v5 0/7] target/riscv: Add support for Control Transfer Records Ext.

re is the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v5 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux k

[PATCH v5 4/7] target/riscv: Add support to record CTR entries.

This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal

[PATCH v5 1/7] target/riscv: Remove obsolete sfence.vm instruction

Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Jason Chien --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v5 2/7] target/riscv: Add Control Transfer Records CSR definitions.

/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5 Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu_bits.h | 94 + 1 file changed, 94 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v5 7/7] target/riscv: machine: Add Control Transfer Record state description

Add a subsection to machine.c to migrate CTR CSR state Signed-off-by: Rajnesh Kanwal --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index e1bdc31c7c53a8a4f539113d501c8e46f7a914e9

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