This series enables Control Transfer Records extension support on riscv platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and this series is based on v1.0_rc6 [0]
CTR extension depends on both the implementation of S-mode and Sscsrind extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using sscsrind extension. The series is based on Smcdeleg/Ssccfg counter delegation extension [2] patches [3]. CTR itself doesn't depend on counter delegation support. This rebase is basically to include the Smcsrind patches. Here is the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v3 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux kernel patches can be found here: https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2 [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc6 [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0 [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 [3]: https://lore.kernel.org/all/20240217000134.3634191-1-ati...@rivosinc.com/ [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine Changelog: v3: Improvements based on Jason Chien and Frank Chang's feedback. - Created single set of MACROs for CTR CSRs in cpu_bit.h - Some fixes in riscv_ctr_add_entry. - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range. - Improved extension dependency check. - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze. - Added implied rules for Smctr and Ssctr. - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops. - Some more cosmetic changes. v2: Lots of improvements based on Jason Chien's feedback including: - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz. - Fixed and added more CTR extension enable checks. - Fixed CTR CSR predicate functions. - Fixed external trap xTE bit checks. - One fix in freeze function for VS-mode. - Lots of minor code improvements. - Added checks in sctrclr instruction helper. - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkan...@rivosinc.com/ v1: - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkan...@rivosinc.com/ --- Rajnesh Kanwal (6): target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support to record CTR entries. target/riscv: Add CTR sctrclr instruction. target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. target/riscv/cpu.c | 26 ++- target/riscv/cpu.h | 13 ++ target/riscv/cpu_bits.h | 94 ++++++++ target/riscv/cpu_cfg.h | 2 + target/riscv/cpu_helper.c | 266 ++++++++++++++++++++++ target/riscv/csr.c | 294 ++++++++++++++++++++++++- target/riscv/helper.h | 9 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_privileged.c.inc | 22 +- target/riscv/insn_trans/trans_rvi.c.inc | 31 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 20 ++ target/riscv/op_helper.c | 155 ++++++++++++- target/riscv/tcg/tcg-cpu.c | 11 + target/riscv/translate.c | 10 + 14 files changed, 941 insertions(+), 14 deletions(-) --- base-commit: 27dec0a099f70f309d89b43122409aeb003d5702 change-id: 20241029-b4-ctr_upstream_v3-7ab764c68bf1 -- Regards, Rajnesh Kanwal
