Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips
From: Yongbok Kim
Reuse CP0_CHECK macro for gen_m{f|t}hc0.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 46 +-
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/target
physical address bounds specified by MAAR.
As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 4
target-mips/hel
On 25/03/16 12:50, Aleksandar Markovic wrote:
>
> /*
> | The pattern for a default generated single-precision NaN.
>
> **/
> +float32 float32_
On 25/03/16 12:50, Aleksandar Markovic wrote:
> +#define MSA_CLASS_SIGNALING_NAN 0x001
> +#define MSA_CLASS_QUIET_NAN 0x002
> +#define MSA_CLASS_NEGATIVE_INFINITY 0x004
> +#define MSA_CLASS_NEGATIVE_NORMAL0x008
> +#define MSA_CLASS_NEGATIVE_SUBNORMAL 0x010
> +#define MSA_CLASS_NE
Fix off-by-one error in ITC Tag read.
Remove the switch as we just want to check if index is in valid range
rather than test against list of values.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/misc
On 03/04/16 15:25, Aleksandar Markovic wrote:
> It just seems to me that, in similar case, 16-bit default NaN value should be
> 0x7E00. This value is needed for MSA operations. ("MIPS Architecture for
> Programmers Volume IV-j: The MIPS32® SIMD Architecture Module", Revision
> 1.12, (february 3,
Fix off-by-one error in ITC Tag read.
Remove the switch as we just want to check if index is in valid range
rather than test against list of values.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/misc
9:26 +0100)
MIPS patches 2016-04-08
Changes:
* fix off-by-one error in ITU
----
Leon Alrae (1):
hw/mips_itu: fix off-by-one reported by Coverity
hw/misc/mips_itu.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
On 12/04/16 13:58, Aleksandar Markovic wrote:
> @@ -322,14 +327,14 @@ int float32_is_quiet_nan( float32 a_ )
> | NaN; otherwise returns 0.
>
> **/
>
> -int float32_is_signaling_nan( float32 a_ )
> +int float32_is_signa
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct default NaN values (in their 16-, 32-, and 64-bit flavors).
>
> For more info, see [1], page 84, Table 6.3 "Value Supplied When
> a New Qu
N) {
> -return 2;
> -} else if (aIsQNaN) {
> -return 0;
Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?
Otherwise:
Reviewed-by: Leon Alrae
> +if (stat
it a/target-mips/translate.c b/target-mips/translate.c
> index de0b224..1d376fc 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1434,6 +1434,8 @@ typedef struct DisasContext {
> bool vp;
> bool cmgcr;
> bool mrp;
> +bool abs2008;
> +
Blank line. Otherwise:
Reviewed-by: Leon Alrae
Regards,
Leon
On 12/04/2016 13:58, Aleksandar Markovic wrote:
> @@ -3200,11 +3200,17 @@ FLOAT_RINT(rint_d, 64)
> #define FLOAT_CLASS_POSITIVE_ZERO 0x200
>
> #define FLOAT_CLASS(name, bits) \
> -uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)\
>
On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks
> to me that "fst" should be called "status" instead (just not to break
> consistency throughout SoftFloat library and in other places of assigning
> name "status" to the l
tion is passed to the inner guest.
>
> Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> Signed-off-by: James Hogan
> Cc: Leon Alrae
> Cc: Yongbok Kim
> Cc: Aurelien Jarno
> ---
> target-mips/op_helper.c | 16
> 1
f counter, which is disabled in the outer guest's CP0_HWREna by
KVM so it can emulate the inner guest's counter. The emulation fails and
the RI exception is passed to the inner guest.
Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
Signed-off-by: James Hog
Hi,
Just a single bug-fix for 2.6 if possible.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit f419a626c76bcb26697883af702862e8623056f9:
usb/uhci: move pid check (2016-04-25 12:05:05 +0100)
are available in the git repository at:
git://github.com/la
On 18/04/16 17:03, Aleksandar Markovic wrote:
> -#if SNAN_BIT_IS_ONE
> -return ((uint32_t)(a << 1) >= 0xff80);
> -#else
> -return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003F );
> -#endif
> +if (status->snan_bit_is_one) {
> +return ((uint32_t)(a << 1) >= 0xFF80
return const_float32(0xFFC0);
> +#endif
> }
> #endif
> }
> @@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
> if (status->snan_bit_is_one) {
> return const_float64(LIT64(0x7FF7));
> } else {
> +#if defined(TARGET_MIPS)
> +return const_float64(LIT64(0x7FF8));
> +#else
> return const_float64(LIT64(0xFFF8));
> +#endif
> }
> #endif
> }
Reviewed-by: Leon Alrae
On 18/04/16 17:03, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Amend definitions of some Mips processors related to FCR31
> (float status control register). Most significantly, FCR31 of
> processors mips32r6-generic, mips64r6-generic, and P5600 will
> be set so that its FCR31_ABS20
On 18/04/16 17:03, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Functions mips_cpu_reset() and msa_reset() are updated so that flag
> snan_bit_is_one is properly set for any Mips FPU/MSA configuration.
> For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke
> set_snan_b
On 18/04/16 17:03, Aleksandar Markovic wrote:
> @@ -3049,6 +3050,330 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env,
> uint32_t fst0)
> return wt2;
> }
>
> +uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
> +{
> +uint64_t dt2;
> +
> +dt2 = float64_to_int64
On 24/02/16 14:20, Yongbok Kim wrote:
> The MAAR register is a read/write register included in Release 5
> of the architecture that defines the accessibility attributes of
> physical address regions. In particular, MAAR defines whether an
> instruction fetch or data load can speculatively access a
ound. Try passing init= option
to kernel. See Linux Documentation/init.txt for guidance.
Therefore always indicate presence of 2008-NaN support in R6 as well as in
R5+MSA CPUs, even though this feature is not yet supported by MIPS in QEMU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h
Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak
files to avoid having to repeat CONFIG defines four times.
Suggested-by: Peter Maydell
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu-common.mak | 32
default-configs/mips
mak (2016-03-23 13:36:56 +)
MIPS patches 2016-03-23
Changes:
* add mips-softmmu-common.mak
* indicate presence of IEEE 754-2008 FPU in MIPS64R6-generic and P5600
-------
also on reset to disable the block
Leon Alrae (8):
hw/mips: implement ITC Configuration Tags and Storage Cells
hw/mips: implement ITC Storage - Control View
hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
hw/mips: implement ITC Storage - P/V Sync and Try Views
hw
is 0. P/V Try View does not block the thread, it returns 0 in this case.
Cell's Empty and Full bits are not modified.
Trap bit (i.e. Gating Storage exceptions) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 68 ++
1
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void
Storage contains
both types of cells then FIFOs are located before Semaphores.
Since issuing thread can get blocked on the access to a cell (in E/F
Synchronized and P/V Synchronized Views) each cell has a bitmap to track
which threads are currently blocked.
Signed-off-by: Leon Alrae
---
default
Control view is used to access the ITC Storage Cell Tags. It never causes
the issuing thread to block.
Guest can empty the FIFO cell by setting Empty bit to 1.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 104 +
1 file changed, 104
tions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 113 +
1 file changed, 113 insertions(+)
diff --git a/hw/misc/mips_itu.c
Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.
Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 27
the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 +-
target-mips/helper.h| 3 +++
target-mips
Make ITU available in the system if CPU supports multithreading
and is part of CPS.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 32
include/hw/mips/cps.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index
Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips
Make ITU available in the system if CPU supports multithreading
and is part of CPS.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 32
include/hw/mips/cps.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index
tions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 113 +
1 file changed, 113 insertions(+)
diff --git a/hw/misc/mips_itu.c
via CPC memory-mapped registers.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c| 16 +
hw/misc/mips_cmgcr.c | 53
include/hw/mips/cps.h| 2 ++
include/hw/misc/mips_cmgcr.h | 10 +
4 files changed, 81
on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void
use
the same pin numbers as before.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c| 60 -
target-mips/cpu.h | 1 +
target-mips/translate.c | 10 +
3 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/hw/mips/mips_m
Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index f5173c4..cbfdb78
} to mips_cmgcr.{c,h},
* replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs| 1 +
hw/misc/mips_cmgcr.c | 106 +++
include/hw/misc/mips_cmgcr.h | 49
3 files changed, 156
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.
These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.
Signed-off-by: Leon
Control view is used to access the ITC Storage Cell Tags. It never causes
the issuing thread to block.
Guest can empty the FIFO cell by setting Empty bit to 1.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 104 +
1 file changed, 104
CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/translate.c | 18 ++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4f3ebb9..55d3224 100644
--- a/target-mips
Changes:
* add initial MIPS CPS support
* implement ITU block
* implement MAAR
----
Leon Alrae (17):
hw/mips: implement generic MIPS Coherent Processing System container
hw/mips/cps: create GCR block inside CPS
hw/mi
Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.
Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 27
From: Yongbok Kim
Reuse CP0_CHECK macro for gen_m{f|t}hc0.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 46 +-
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/target
is 0. P/V Try View does not block the thread, it returns 0 in this case.
Cell's Empty and Full bits are not modified.
Trap bit (i.e. Gating Storage exceptions) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 68 ++
1
the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 +-
target-mips/helper.h| 3 +++
target-mips
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 23 +++
include/hw/mips/cps.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 782aa2b..cfd808d 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -61,6 +61,8 @@ static void
Storage contains
both types of cells then FIFOs are located before Semaphores.
Since issuing thread can get blocked on the access to a cell (in E/F
Synchronized and P/V Synchronized Views) each cell has a bitmap to track
which threads are currently blocked.
Signed-off-by: Leon Alrae
---
default
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 68 ++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index b70948d..9e8b9ce 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips
physical address bounds specified by MAAR.
As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 4
target-mips/hel
Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu-common.mak | 1
ch.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target-mips/helper.h| 18 +--
> target-mips/op_helper.c | 369
> +++++---
> target-mips/translate.c | 122 +---
> 3 files changed, 461 insertions(+), 48 deletions(-)
Reviewed-by: Leon Alrae
> - Add preprocessor constants for all bits of FCR31 and related masks
> for its subfields.
Introducing all these constants for fcr31_rw_bitmask doesn't seem necessary
or useful
>
> - Modify handling of CFC1 and CTC1 instructions (cases 25, 26, 28)
> so that they utilize newly-defind constan
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index e934884..2cdd2bd 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
> env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
> env->
same patch:
http://wiki.qemu.org/Contribute/SubmitAPatch#Don.27t_include_irrelevant_changes
If you drop the adjustment of surrounding code then feel free to add:
Reviewed-by: Leon Alrae
Thanks,
Leon
>
> Signed-off-by: Thomas Schwinge
> Signed-off-by: Maciej W. Rozycki
> Signe
/translate_init.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Leon Alrae
> @@ -110,9 +110,11 @@ struct CPUMIPSFPUContext {
> #define FCR0_PRID 8
> #define FCR0_REV 0
> /* fcsr */
> +uint32_t fcr31_rw_bitmask;
> uint32_t fcr31;
> -#define FCR31_ABS2008 19
> -#define FCR31_NAN2008 18
> +#define FCR31_NAN2008 18
> +#define FCR31_ABS2008 19
Now the
:
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06223.html
Thanks,
Leon
Leon Alrae (3):
target-mips: add exception base to MIPS CPU
hw/mips_cpc: make VP correctly start from the reset vector
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/misc/mips_cmgcr.c
CPU_INTERRUPT_HALT to halt a VP.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd..6d34574 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void
Replace hardcoded 0xbfc0 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2
will start execution.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cmgcr.c | 54 +++-
include/hw/misc/mips_cmgcr.h | 18 +++
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index e6cf17
t; target-mips/gdbstub.c| 8 +++-
> target-mips/op_helper.c | 14 +++---
> target-mips/translate.c | 5 ++---
> target-mips/translate_init.c | 26 ++
> 6 files changed, 56 insertions(+), 19 deletions(-)
Reviewed-by: Leon Alrae
t-mips/cpu.h | 5 +
> target-mips/helper.h | 4 +-
> target-mips/msa_helper.c | 88 +++
> target-mips/op_helper.c | 17 +-
> target-mips/translate.c | 5 +-
> target-mips/translate_init.c | 2 +
> target-ppc/fpu_helper.c |
| 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Leon Alrae
On Fri, Jun 10, 2016 at 09:12:12PM +0100, Maciej W. Rozycki wrote:
> On Fri, 10 Jun 2016, Aleksandar Markovic wrote:
>
> > The changes that make QEMU behavior the same as hardware behavior (in
> > relation to CEIL, CVT, FLOOR, ROUND, TRUNC Mips instructions) are
> > already contained in this pat
On Thu, Jun 23, 2016 at 04:46:14PM +0100, Peter Maydell wrote:
> On 10 June 2016 at 10:57, Aleksandar Markovic
> wrote:
> > From: Aleksandar Markovic
> >
> > This patch series provides number of IEEE 754-2008-related features to
> > Mips platform. It addresses the most sensitive changes that requ
tion by element size
> [-Wmemset-elt-size]
>
> This is indeed correct and due to a wrong usage of sizeof(). Fix that.
>
> Cc: Stefan Weil
> Cc: Leon Alrae
> LP: https://bugs.launchpad.net/qemu/+bug/1577841
> Signed-off-by: Aurelien Jarno
> ---
> target-mips/helper.
On Thu, May 05, 2016 at 01:46:13PM +0100, Peter Maydell wrote:
> On 5 May 2016 at 04:04, xiaoqiang zhao wrote:
> > * Drop the old SysBus init function and use instance_init
> > * Move graphic_console_init into realize stage
> >
> > Signed-off-by: xiaoqiang zhao
> > ---
> > hw/display/jazz_led.c
Hi,
Just two patches in the first target-mips pullreq for 2.7.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit bfc766d38e1fae5767d43845c15c79ac8fa6d6af:
Update version for v2.6.0 release (2016-05-11 16:44:26 +0100)
are available in the git repository a
and due to a wrong usage of sizeof(). Fix that.
Cc: Stefan Weil
Cc: Leon Alrae
Cc: qemu-sta...@nongnu.org
LP: https://bugs.launchpad.net/qemu/+bug/1577841
Signed-off-by: Aurelien Jarno
Reviewed-by: Stefan Weil
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 2 +-
1
From: "xiaoqiang.zhao"
* Drop the old SysBus init function and use instance_init
* Move graphic_console_init into realize stage
Signed-off-by: xiaoqiang zhao
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
hw/display/jazz_led.c | 18 +++---
1 file changed, 11
On 01/05/2015 16:43, Peter Maydell wrote:
>> +#if !defined(CONFIG_USER_ONLY)
>> +static bool cpu_mips_validate_msa_block_access(CPUMIPSState *env,
>> +target_ulong address, int df, int
>> rw)
>> +{
>> +int i;
>> +for (i = 0; i < DF_ELEMENTS(df); i++)
On 01/05/15 16:24, Yongbok Kim wrote:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all the addresses for the operation.
As far as I can tell mips_cpu_do_unaligned_acce
Remove extern int semihosting_enabled declaration from sysemu.h and
create equivalent semihosting_enabled() function. Also introduce
semihost.h containing things related to semihosting config.
Suggested-by: Peter Maydell
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 32
Group semihosting config related variables in a single structure.
Signed-off-by: Leon Alrae
---
vl.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/vl.c b/vl.c
index a42f127..82586c7 100644
--- a/vl.c
+++ b/vl.c
@@ -1227,17 +1227,21 @@ static
Follow the semihosting_enabled() approach and move semihosting_target
related stuff to semihost.h.
Signed-off-by: Leon Alrae
---
gdbstub.c | 8
include/exec/gdbstub.h | 6 --
include/exec/semihost.h | 12
vl.c| 6 ++
4 files
Add new "arg" sub-argument to the --semihosting-config allowing to pass
multiple input argument separately. It is required for example by UHI
semihosting to construct argc and argv.
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 12
qemu-options.hx
hey can be accessed via
include/exec/semihost.h introduced in this patch series.
Since this touches generic semihosting code I'm sending it as a separate
patchset from MIPS-specific UHI semihosting patches.
Regards,
Leon
Leon Alrae (4):
semihosting: remove semihosting_enabled declaratio
On 06/05/2015 16:22, Liviu Ionescu wrote:
>
> apparently your patch does not fix the arm semihosting problems. do you plan
> a separate patch for this?
This patchset doesn't contain any target semihosting specific changes
(just a clean up and new arg option). I'm going to follow up with UHI
patc
On 07/05/2015 07:51, Liviu Ionescu wrote:
>
>> On 06 May 2015, at 17:57, Leon Alrae wrote:
>>
>> +static int add_semihosting_arg(const char *name, const char *val, void
>> *opaque)
>> +{
>> +SemihostingConfig *s = opaque;
>> +if (st
Add new "arg" sub-argument to the --semihosting-config allowing to pass
multiple input argument separately. It is required for example by UHI
semihosting to construct argc and argv.
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 12
qemu-options.hx
stuff from target specific semihosting
code.
Signed-off-by: Leon Alrae
---
gdbstub.c | 8
include/exec/gdbstub.h| 6 --
include/exec/semihost.h | 44
include/sysemu/sysemu.h | 1 -
target-arm/helper.c | 7
difications are relatively simple anyway).
Leon Alrae (2):
semihosting: create SemihostingConfig structure and semihost.h
semihosting: add --semihosting-config arg sub-argument
gdbstub.c | 8 +++---
include/exec/gdbstub.h| 6
include/exec/se
On 07/05/2015 12:50, Liviu Ionescu wrote:
>
>> On 07 May 2015, at 12:52, Leon Alrae wrote:
>>
>>> is it that difficult to count the "arg"s and correctly alloc the array?
>>
>> This probably would require going through the list twice
>
> the
On 07/05/2015 13:35, Liviu Ionescu wrote:
>
>> On 07 May 2015, at 15:21, Leon Alrae wrote:
>>
>> On 07/05/2015 12:50, Liviu Ionescu wrote:
>>>
>>>> On 07 May 2015, at 12:52, Leon Alrae wrote:
>>>>
>>>>> is it that diffic
On 07/05/2015 14:02, Peter Maydell wrote:
>> +static int add_semihosting_arg(const char *name, const char *val, void
>> *opaque)
>> +{
>> +SemihostingConfig *s = opaque;
>> +if (strcmp(name, "arg") == 0) {
>> +s->argc++;
>> +s->argv = g_realloc(s->argv, s->argc * sizeof(voi
doc looks nicer)
v2:
* squash clean-up related patches so renaming is not required (these
modifications are relatively simple anyway).
Leon Alrae (2):
semihosting: create SemihostingConfig structure and semihost.h
semihosting: add --semihosting-config arg sub-argument
gdbstub.c
Add new "arg" sub-argument to the --semihosting-config allowing to pass
multiple input argument separately. It is required for example by UHI
semihosting to construct argc and argv.
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 12
qemu-options.hx
stuff from target specific semihosting
code.
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
gdbstub.c | 8
include/exec/gdbstub.h| 6 --
include/exec/semihost.h | 44
include/sysemu/sysemu.h | 1
Hi Yongbok,
On 11/05/2015 14:15, Yongbok Kim wrote:
> Hi
> I have implemented this to have a flag which isn't that nice.
>
> The thing is that the fact misaligned accesses of MSA LD/ST should be allowed
> in R5 cores
> while all other instructions are not allowed.
> Therefore it is required whic
On 11/05/2015 12:30, Yongbok Kim wrote:
> @@ -391,6 +391,37 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env,
> target_ulong address, int r
> }
> }
>
> +bool cpu_mips_validate_msa_block_access(CPUMIPSState *env, target_ulong addr,
> +int rw, in
From: "Maciej W. Rozycki"
Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
include/exec/softmmu-semi.h | 13 +++--
1 file changed, 7 insertions(+), 6
if semihosting arguments are passed to indicate that the UHI
operations should be used to obtain input arguments.
Still support old-style -kernel/-append if -semihosting-config args have not
been specified.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 9 +-
qemu-options.hx |
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