[PATCH 12/39] target/hexagon: Add implementation of cycle counters

From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 25 ++--- target/hexagon/translate.h | 2 ++ target/hexagon/cpu_helper.c | 12 +--- target/hexagon/translate.c | 27 +++ 4 files

[PATCH 05/39] target/hexagon: Implement modify SSR

From: Brian Cain The per-vCPU System Status Register controls many modal behaviors of the system architecture. When the SSR is updated, we trigger the necessary effects for interrupts, privilege/MMU, and HVX context mapping. Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 100

[PATCH 35/39] target/hexagon: Define gen_precise_exception()

From: Brian Cain Add PC to raise_exception helper Replace the fGEN_TCG_J2_trap0 macro override with the fTRAP()-generated system helper instead. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 7 --- target/hexagon/helper.h| 2 +- target/hexagon/op_helper.c | 10

[PATCH 38/39] target/hexagon: Add guest reg reading functionality

From: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.c | 19 ++- target/hexagon/op_helper.c | 19 +-- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c in

[PATCH 35/38] target/hexagon: Add IRQ events

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_bits.h | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 5d26815eb9..b559a7ba88 100644 --- a/target/hexagon/cpu_bits.h +++ b

[PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 +++ target/hexagon/cpu.c | 73 2 files changed, 78 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 045581d7be..d28c1249f3 100644 --- a/target

[PATCH 32/39] target/hexagon: Define system, guest reg names

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 2 ++ target/hexagon/cpu.c | 29 + 2 files changed, 31 insertions(+) diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 120cfde7b9..fd2397b9ef 100644 --- a/target

[PATCH 09/39] target/hexagon: Implement arch_get_system_reg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index e0dd120cd4..0b0802bfb9 100644 --- a/target/hexagon/cpu_helper.c +++ b/target

[PATCH 13/38] target/hexagon: Define DCache states

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_bits.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 6582bb4f16..5d26815eb9 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -41,6

[PATCH 25/38] target/hexagon: Add TCG overrides for thread ctl

From: Brian Cain Define TCG overrides for start, stop, wait, resume instructions. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 18 ++ target/hexagon/helper.h | 4 target/hexagon/op_helper.c | 20 3 files changed, 42 insertions

[PATCH 04/38] target/hexagon: Make gen_exception_end_tb non-static

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 2 ++ target/hexagon/translate.c | 9 - 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d251e2233f..2bd125297a 100644 --- a/target

[PATCH 13/39] target/hexagon: Implement modify_syscfg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 51 +- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 03bed11f6e..42805d0f1d 100644 --- a/target/hexagon

[PATCH 01/38] docs: Add hexagon sysemu docs

From: Brian Cain Signed-off-by: Brian Cain --- MAINTAINERS| 2 + docs/devel/hexagon-sys.rst | 106 + docs/devel/index-internals.rst | 1 + docs/system/hexagon/cdsp.rst | 10 docs/system/target-hexagon.rst | 100

[PATCH 10/38] target/hexagon: Add TCG values for sreg, greg

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 7 +++ target/hexagon/translate.c | 7 +++ 2 files changed, 14 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 2bd125297a..f611c854dc 100644 --- a/target/hexagon

[PATCH 24/38] target/hexagon: Add TCG overrides for int handler insts

From: Brian Cain Define TCG overrides for {c,}swi {c,s}iad, iassign{r,w}, {s,g}etimask instructions. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 ++ target/hexagon/helper.h | 8 target/hexagon/op_helper.c | 40

[PATCH 37/38] target/hexagon: Define f{S,G}ET_FIELD macros

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/macros.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index b0e9610d98..afbbe8e265 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -649,6

[PATCH 38/38] target/hexagon: Add hex_interrupts support

From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Sid Manning Co-authored-by: Michael Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/hex_interrupts.h | 15 ++ target/hexagon/cpu.c| 2 + target/hexagon

[PATCH 28/38] target/hexagon: Initialize htid, modectl regs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 36a93cc22f..2b6a707fca 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -26,6 +26,7 @@ #include &quo

[PATCH 16/38] target/hexagon: Add placeholder greg/sreg r/w helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/helper.h| 9 + target/hexagon/op_helper.c | 34 ++ 2 files changed, 43 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index f8baa599c8..fddbd99a19 100644

[PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 29 + 1 file changed, 29 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a548d575a7..9f4cfd03c4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -489,6

[PATCH 08/39] target/hexagon: Implement get_exe_mode()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/reg_fields_def.h.inc | 11 +++ target/hexagon/cpu_helper.c | 24 2 files changed, 35 insertions(+) diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc

[PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/translate.h | 2 + target/hexagon/genptr.c| 7 +- target/hexagon/translate.c | 142 - 4 files changed, 132 insertions(+), 21 deletions(-) diff --git a

[PATCH 26/39] target/hexagon: Decode trap1, rte as COF

From: Brian Cain Also: handle rte instructions at the end of the packet. Signed-off-by: Brian Cain --- target/hexagon/decode.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 23deba2426..5d0beeeaf2 100644 --- a/target

[PATCH 14/39] target/hexagon: Add system event, cause codes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 10 ++- target/hexagon/cpu_bits.h | 55 --- 2 files changed, 49 insertions(+), 16 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 7e2ea838c5

[PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 133 ++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e9f24581a6..a548d575a7 100644 --- a/target/hexagon/cpu.c +++ b

[PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index d0dc4afac7..f3ffac81b6 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon

[PATCH 07/39] target/hexagon: Implement wait helper

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 40 + target/hexagon/op_helper.c | 6 +- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.h b

[PATCH 17/39] target/hexagon: Implement software interrupt

From: Brian Cain Co-authored-by: Mike Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 - target/hexagon/hexswi.h| 17 +++ target/hexagon/cpu.c | 2 + target/hexagon/hexswi.c| 258 + target/hexagon/op_helper.c | 1

[PATCH 17/38] target/hexagon: Add vmstate representation

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 4 target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 + 3 files changed, 32 insertions(+) create mode 100644 target/hexagon/machine.c diff --git a/target/hexagon

[PATCH 37/39] target/hexagon: Add support for loadw_phys

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 3 +++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/ldst.idef | 3 +++ 3 files changed, 7 insertions(+) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py

[PATCH 26/38] target/hexagon: Add TCG overrides for rte, nmi

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 19 +++ target/hexagon/helper.h | 1 + target/hexagon/op_helper.c | 4 3 files changed, 24 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index

[PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 6d73a18db4..e56553462f 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b

[PATCH 30/38] target/hexagon: Add a TLB count property

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/max.h | 26 ++ target/hexagon/cpu.c | 4 3 files changed, 31 insertions(+) create mode 100644 target/hexagon/max.h diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h

[PATCH 01/39] target/hexagon: Implement ciad helper

From: Brian Cain ciad is the clear interrupt auto disable instruction. This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf See §11.9.2 S

[PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/sys_macros.h | 8 +-- target/hexagon/op_helper.c | 104 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index

[PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 9f79b1a20c..83088cfaa3 100644 --- a/target/hexagon

[PATCH 20/38] target/hexagon: Implement do_raise_exception()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 5 + target/hexagon/op_helper.c | 20 2 files changed, 25 insertions(+) diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 9658141316..7cf7bcaa6c 100644 --- a/target

[PATCH 02/39] target/hexagon: Implement {c,}swi helpers

From: Brian Cain {c,}swi are the "software interrupt"/"Cancel pending interrupts" instructions. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexag

[PATCH 07/38] target/hexagon: Add a placeholder fp exception

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/arch.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index d053d68487..87c2f6a53f 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -208,6 +208,11 @@ void

[PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers

From: Brian Cain iassign{r,w} are the "Interrupt to thread assignment {read,write}" instructions. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_

[PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 1 + target/hexagon/translate.c | 99 +- 2 files changed, 99 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 9bc4b3ce8b

[PATCH 32/38] target/hexagon: Add stubs for modify_ssr/get_exe_mode

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 2 ++ target/hexagon/cpu_helper.c | 8 2 files changed, 10 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 5f5f15149a..e0c0c037a6 100644 --- a/target/hexagon

[PATCH 11/39] target/hexagon: Add representation to count cycles

From: Brian Cain The PCYCLE register can be enabled to indicate accumulated clock cycles. Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 3 ++- target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 - 3 files changed, 29 insertions(+), 2 deletions

[PATCH 36/38] target/hexagon: Add clear_wait_mode() definition

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index e0c0c037a6..6f0c6697ad 100644 --- a/target/hexagon

[PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index d2297c036d..07ad8e9616 100644 --- a/target/hexagon/hex_mmu.c +++ b

[PATCH 11/38] target/hexagon: Add guest/sys reg writes to DisasContext

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 36 1 file changed, 36 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index f611c854dc..0eaa3db03e 100644 --- a/target/hexagon/translate.h +++ b

[PATCH 15/38] target/hexagon: Add handlers for guest/sysreg r/w

From: Brian Cain This commit provides handlers to generate TCG for guest and system register reads and writes. They will be leveraged by a future commit. Signed-off-by: Brian Cain --- target/hexagon/genptr.c | 159 1 file changed, 159 insertions

[PATCH 21/38] target/hexagon: Add system reg insns

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/macros.h | 2 + target/hexagon/hex_common.py | 15 +- target/hexagon/imported/encode_pp.def | 213 +++-- target/hexagon/imported/system.idef | 262 +++--- 4 files

[PATCH 09/38] target/hexagon: Add guest, system reg number state

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 8 target/hexagon/cpu.c | 17 + 2 files changed, 25 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 20ea0adcca..b7789a3c90 100644 --- a/target/hexagon/cpu.h +++ b

[PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/helper.h| 3 +++ target/hexagon/op_helper.c | 20 2 files changed, 23 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 730eaf8b9a..3df663baeb 100644 --- a/target/hexagon

[PATCH 29/38] target/hexagon: Add locks, id, next_PC to state

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 37 +++-- target/hexagon/cpu.c | 6 ++ target/hexagon/machine.c | 4 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon

[PATCH 00/39] hexagon system emu, part 2/3

this series. Brian Cain (38): target/hexagon: Implement ciad helper target/hexagon: Implement {c,}swi helpers target/hexagon: Implement iassign{r,w} helpers target/hexagon: Implement start/stop helpers target/hexagon: Implement modify SSR target/hexagon: Implement {g,s}etimask helpers

[PATCH 00/38] hexagon system emu, part 1/3

Hexagon Virtual Machine Specification. [1] https://github.com/quic/hexagonMVM Brian Cain (38): docs: Add hexagon sysemu docs docs/system: Add hexagon CPU emulation target/hexagon: Add System/Guest register definitions target/hexagon: Make gen_exception_end_tb non-static target/hexagon: Switc

[PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.c | 20 1 file changed, 20 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index ff881d1060..248ed60f29 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon

[PATCH 21/39] target/hexagon: Implement hexagon_resume_threads()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 37 + target/hexagon/op_helper.c | 3 ++- 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a

[PATCH 27/38] target/hexagon: Add sreg_{read,write} helpers

From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 8 +++ target/hexagon/cpu.c| 1 + target/hexagon/cpu_helper.c | 37 target/hexagon/op_helper.c | 114 ++-- 4 files changed, 156

[PATCH 03/38] target/hexagon: Add System/Guest register definitions

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py | 21 +++- target/hexagon/hex_common.py| 163 2 files changed, 181 insertions(+), 3 deletions(-) diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon

[PATCH 18/38] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index db50defeb6..7fb11a0819 100755 --- a/target/hexagon/hex_common.py +++ b/target

[PATCH 2/8] hw/hexagon: Add machine configs for sysemu

From: Brian Cain Co-authored-by: Mike Lambert Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- MAINTAINERS| 2 + qapi/machine.json | 2 +- include/hw/hexagon/hexagon.h | 151 + hw/hexagon

[PATCH 1/8] hw/intc: Add l2vic interrupt controller

From: Sid Manning Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain --- MAINTAINERS| 2 + docs/devel/hexagon-l2vic.rst | 59 + docs/devel/index-internals.rst | 1 + include/hw/intc/l2vic.h| 37 +++ hw

[PATCH 5/8] hw/hexagon: Modify "Standalone" symbols

From: Brian Cain These symbols are used by Hexagon Standalone OS to indicate whether the program should halt and wait for interrupts at startup. For QEMU, we want these programs to just continue crt0 startup through to the user program's main(). Signed-off-by: Brian Cain --- hw/he

[PATCH 7/8] hw/hexagon: Define hexagon "virt" machine

From: Brian Cain Signed-off-by: Brian Cain --- configs/devices/hexagon-softmmu/default.mak | 1 + configs/targets/hexagon-softmmu.mak | 1 + include/hw/hexagon/virt.h | 41 ++ hw/hexagon/virt.c | 395 target/hexagon

[PATCH 3/8] hw/hexagon: Add v68, sa8775-cdsp0 defs

From: Brian Cain Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 64 ++ hw/hexagon/machine_cfg_v68n_1024.h.inc| 65 +++ 2 files changed, 129 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc create

[PATCH 0/8] hexagon system emu, part 3/3

uction set simulator included with the Hexagon SDK. These programs generally depend on semihosting support, which will come later. Brian Cain (6): hw/hexagon: Add machine configs for sysemu hw/hexagon: Add v68, sa8775-cdsp0 defs hw/hexagon: Modify "Standalone" symbols target/hexag

[PATCH 8/8] tests/functional: Add a hexagon minivm test

From: Brian Cain Signed-off-by: Brian Cain --- MAINTAINERS | 1 + tests/functional/meson.build| 8 + tests/functional/test_hexagon_minivm.py | 42 + 3 files changed, 51 insertions(+) create mode 100755 tests/functional

[PATCH 6/8] target/hexagon: add build config for softmmu

Signed-off-by: Brian Cain --- MAINTAINERS | 1 + configs/devices/hexagon-softmmu/default.mak | 7 +++ configs/targets/hexagon-softmmu.mak | 6 ++ target/Kconfig | 1 + target/hexagon/Kconfig | 2

[PATCH 22/38] target/hexagon: Add sysemu TCG overrides

From: Brian Cain Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}). Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 32 target/hexagon/gen_tcg_sys.h | 41 target/hexagon/helper.h | 1 + target/hexagon

[PATCH 4/8] hw/hexagon: Add support for cfgbase

From: Sid Manning Signed-off-by: Sid Manning --- target/hexagon/cpu.h | 1 + hw/hexagon/hexagon_dsp.c | 10 ++ target/hexagon/cpu.c | 6 ++ 3 files changed, 17 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 73c3bb34b0..0608d3265c 100644 --- a

[PATCH 19/38] target/hexagon: Define register fields for system regs

From: Brian Cain Define the register fields for ssr, schedcfg, stid, bestwait, ccr, modectl, imask, ipendad. Define the fields for TLB entries. Signed-off-by: Brian Cain --- target/hexagon/reg_fields_def.h.inc | 96 + 1 file changed, 96 insertions(+) diff --git a

Re: [PATCH] tests/tcg: Suppress compiler false-positive warning on sha1.c

On 3/4/2025 6:51 AM, Peter Maydell wrote: On Tue, 4 Mar 2025 at 11:56, Alex Bennée wrote: Peter Maydell writes: +# GCC versions 12/13/14/15 at least incorrectly complain about +# "'SHA1Transform' reading 64 bytes from a region of size 0"; see the gcc bug +# https://gcc.gnu.org/bugzilla/show

Re: [PATCH 8/8] tests/functional: Add a hexagon minivm test

On 3/5/2025 2:05 AM, Thomas Huth wrote: On 04/03/2025 16.46, Philippe Mathieu-Daudé wrote: Hi Brian, On 1/3/25 18:20, Brian Cain wrote: From: Brian Cain A bit opaque... Signed-off-by: Brian Cain ---   MAINTAINERS |  1 +   tests/functional/meson.build

Re: QEMU and ia64

On 3/5/2025 2:37 AM, Benjamin Charlton wrote: Hello. Sorry to bother you, I am very new to all of this and but I am looking for a ia64 emulator, sadly it has to be this to run a piece of old software. GPT suggested I clone your project and emulate this processor. However I am receiving an e

Re: [PATCH 8/8] tests/functional: Add a hexagon minivm test

On 3/4/2025 10:15 AM, Brian Cain wrote: On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote: Hi Brian, On 1/3/25 18:20, Brian Cain wrote: From: Brian Cain A bit opaque... Whoops -- will fix it. Signed-off-by: Brian Cain ---   MAINTAINERS |  1 +   tests

Re: [PATCH 02/38] docs/system: Add hexagon CPU emulation

On 3/5/2025 1:36 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 02/38] docs/system: Add hexagon CPU emulation

On 3/5/2025 3:21 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Wednesday, March 5, 2025 2:13 PM To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org Cc: richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs

On 3/12/2025 2:19 PM, Philippe Mathieu-Daudé wrote: On 1/3/25 06:26, Brian Cain wrote: From: Brian Cain Signed-off-by: Brian Cain ---   target/hexagon/cpu.c | 8   1 file changed, 8 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 36a93cc22f..2b6a707fca

Re: [PATCH 1/6] target/hexagon: handle .new values

On 4/4/2025 8:25 AM, Matheus Tavares Bernardino wrote: On Thu, 3 Apr 2025 19:51:58 -0700 Brian Cain wrote: From: Brian Cain Perhaps it would be best to reset the autorship here to brian.c...@oss.qualcomm.com? Good catch -- will do. Signed-off-by: Brian Cain --- target/hexagon

Re: [PATCH] target/hexagon: Implement CPUState.mmu_index

On 4/3/2025 10:49 AM, Richard Henderson wrote: Signed-off-by: Richard Henderson --- Reviewed-by: Brian Cain target/hexagon/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 766b678651..59fc9ed698 100644 --- a/target

[PATCH 4/6] target/hexagon: s/pkt_has_store/pkt_has_scalar_store

From: Brian Cain To remove any confusion with HVX or other potential store instructions, we'll qualify this context var with "scalar". Signed-off-by: Brian Cain --- target/hexagon/idef-parser/README.rst | 2 +- target/hexagon/insn.h | 4 ++--

[PATCH 2/6] target/hexagon: Fix badva reference, delete CAUSE

From: Brian Cain The BADVA reg is referred to with the wrong identifier. The CAUSE reg field of SSR is not yet modeled. Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index

[PATCH 5/6] target/hexagon: Remove unreachable

From: Brian Cain We should raise an exception in the event that we encounter a packet that can't be correctly decoded, not fault. Signed-off-by: Brian Cain --- target/hexagon/decode.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/hexagon/decode.c b/t

[PATCH 6/6] target/hexagon: Add memory order definition

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b4640..ccaf6a9d28 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h

[PATCH 1/6] target/hexagon: handle .new values

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 758e5fd12d..242dee3731 100755 --- a/target/hexagon

Re: [PATCH v2 0/2] target/hexagon: Fix macOS build

On 4/2/2025 6:42 AM, Anton Johansson wrote: A default macOS build with xcode cli tools installed lacks the `indent` program needed by the idef-parser postprocess step. If `indent` is installed through homebrew it doesn't support the `-linux` flag. Conditionally run `indent` only on linux hosts.

Re: [RFC PATCH] Hexagon (target/hexagon) analyze all reads before writes

On 3/24/2025 9:14 PM, Taylor Simpson wrote: I noticed that analyze_packet is marking the implicit pred reads after marking all the writes. However, the semantics of the instrucion and packet are to do all the reads, then do the operation, then do all the writes. Here is the old code static vo

[PATCH 0/6] misc hexagon patches

While preparing the system emulation patches, these ones stuck out as not-strictly-related to sysemu. We can review and apply them independently of those. Brian Cain (6): target/hexagon: handle .new values target/hexagon: Fix badva reference, delete CAUSE target/hexagon: Add missing A_CALL

[PATCH 3/6] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 242dee3731..85eabc9876 100755 --- a/target/hexagon/hex_common.py +++ b/target

Re: [RFC PATCH] Hexagon (target/hexagon) analyze all reads before writes

. Signed-off-by: Taylor Simpson --- I found no regressions when testing this patch downstream.  I agree that this reordering makes sense regardless of whether we can find a test that fails now. Reviewed-by: Brian Cain Tested-by: Brian Cain target/hexagon/translate.c | 18 +++

Re: [PATCH v2 2/2] target/hexagon: Only indent on linux

On 4/2/2025 6:42 AM, Anton Johansson wrote: indent on macOS, installed via homebrew, doesn't support -linux. Only run indent on linux hosts. Signed-off-by: Anton Johansson --- Reviewed-by: Brian Cain target/hexagon/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 del

Re: [PATCH v2 1/2] target/hexagon: Replace `prepare` script with meson target

` and replace the script with a meson custom_target. Signed-off-by: Anton Johansson --- Reviewed-by: Brian Cain target/hexagon/idef-parser/prepare | 24 target/hexagon/meson.build | 3 ++- 2 files changed, 2 insertions(+), 25 deletions(-) delete mode

Re: [PATCH 2/2] target/hexagon: Drop `ident` postprocess step

On 3/26/2025 7:42 AM, 'Anton Johansson' wrote: On 25/03/25, Brian Cain wrote: On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Anton Johansson Sent: Wednesday, March 12, 2025 2:46 PM To: qemu-devel@nongnu.org Cc: a...@rev.ng; ltaylorsimp...

[PATCH 31/38] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc

From: Brian Cain {TLB,k0}lock counts are used to represent the TLB, k0 locks among hardware threads. wait_next_pc represents the program counter to set when resuming from a wait-for-interrupts state. cause_code contains the precise exception cause.This will be used by subsequent commits

[PATCH 05/38] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_helper_funcs.py | 23 ++- target/hexagon/gen_helper_protos.py | 23 --- target/hexagon/gen_idef_parser_funcs.py | 2 ++ target/hexagon/gen_op_attribs.py| 2 +- target

[PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index e8d89d8526..1cdf4f8dd0 100644 --- a/target/hexagon/cpu_helper.h +++ b

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