From: Brian Cain <bc...@quicinc.com> Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com> --- target/hexagon/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a548d575a7..9f4cfd03c4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -489,6 +489,24 @@ static void find_qemu_subpage(vaddr *addr, hwaddr *phys, int page_size) *phys += offset; } +static hwaddr hexagon_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + CPUHexagonState *env = cpu_env(cs); + hwaddr phys_addr; + int prot; + int page_size = 0; + int32_t excp = 0; + int mmu_idx = MMU_KERNEL_IDX; + + if (get_physical_address(env, &phys_addr, &prot, &page_size, &excp, + addr, 0, mmu_idx)) { + find_qemu_subpage(&addr, &phys_addr, page_size); + return phys_addr; + } + + return -1; +} + #define INVALID_BADVA 0xbadabada @@ -595,6 +613,12 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, } +#include "hw/core/sysemu-cpu-ops.h" + +static const struct SysemuCPUOps hexagon_sysemu_ops = { + .get_phys_page_debug = hexagon_cpu_get_phys_page_debug, +}; + static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUHexagonState *env = cpu_env(cs); @@ -624,6 +648,8 @@ static const TCGCPUOps hexagon_tcg_ops = { #if !defined(CONFIG_USER_ONLY) .cpu_exec_interrupt = hexagon_cpu_exec_interrupt, .tlb_fill = hexagon_tlb_fill, + .cpu_exec_halt = hexagon_cpu_has_work, + .do_interrupt = hexagon_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; @@ -653,9 +679,12 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) cc->gdb_core_xml_file = "hexagon-core.xml"; cc->disas_set_info = hexagon_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops = &hexagon_sysemu_ops; dc->vmsd = &vmstate_hexagon_cpu; #endif +#ifdef CONFIG_TCG cc->tcg_ops = &hexagon_tcg_ops; +#endif } #ifndef CONFIG_USER_ONLY -- 2.34.1