Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 130 +
include/hw/tricore/tricore.h | 54 +
3 files changed, 185 insertions
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Replace OP_MEM_INDIRECT with gen_offset_ld/st functions using TCGMemOp.
- Change load/store instructions to use TCGMemOp.
target-tric
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Change compare to 0 at instructions JZ_T and JNZ_T.
- Group SBC instructions to one case.
- Group SBRN instructions to one case.
target-tricore/translate.c |
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Add one decode function for all SLR instructions.
- Add one decode function for all SRO instructions.
- Remove duplicate SSRO instructions, which were removed in patch v1 15
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Replace gen_ssov with helper for add_ssov and sub_ssov.
- Move SRR instructions to one decode function.
target-tricore/helper.h| 2 +
target-tricore/op_helpe
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Remove AND in ST_B and ST_H instructions.
- Load/Store instructions now use new TCGMemOp.
- Move SSR instructions to one decode function.
target-tricore/translate.c |
e duplicate SSRO instructions.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes f
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Fill in cdc_increment/cdc_decrement
- Replace save/restore_context with s
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Change gen_loop() to subtract first and then compare to -1.
- Change gen_loop() using next_pc insted of insn_bytes.
- Change SBR_LOOP instructions to
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Change cdc_zero using clo32 instead of a loop.
- Change gen_saturate/_h using movecond instead of a bra
+tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
Are you planning to come back to implement V and AV bits later?
Yes. I will do that in the next version of this patchset.
+case OPC1_16_SRC_MOV_A:
+/* load const4 again unsigned */
+const4 = MASK_OP_SRC_CONS
+tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
Are you planning to come back to implement V and AV bits later?
Would you recommend implementing this as a helper? It seems rather
complex. Especially with half-word and byte arithmetic. On the other
hand the instructions using t
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Replace ADD instructions with gen_add_i32 for PSW bit calculation.
- Add gen_sub/mul_i32 for PSW bit calculation
- Replace SUB instructions with gen_sub_i32 for
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Add cache for PSW_USB bits and psw_write/_read functions.
- Add tricore_feature, set_feature functions and enum of cpu features.
- Remove translate_init.c.
- Move init code f
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Fix CDC.COUNT calculation in cdc_zero.
- helper_ret now uses psw_write.
- Add missing temp_free
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Fix CDC.COUNT calculation in cdc_increment/_decrement.
- helper_ret/_call now use psw_r
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 66 +-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 54 ++
1 file changed, 54 insertions(+)
diff --git
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3 files changed, 184 insertions
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59 ++
target-tricore
n_net_tl.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
target
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Add initialization for PSW_USB bits as TCG regs.
- Remove cpu_tricore_init from translate.c (see patch v3[01
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Remove helper_shac, gen_shac
- Remove len parameter of gen_shaci
- Change gen_shaci to a special case.
-
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Remove blank line at the end of the file.
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files chan
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- Replace gen_calc_psw_sv, gen_calc_psw_sav, gen_calc_psw_av calls.
- Rename gen_sub_i32 to gen_sub_d.
- Fix V bit calculation in gen_sub_d and gen_mul_i
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 66 +-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- tricore_cpu_type_info changed to abstract.
- Change documentation of PSW_USB_AV and PSW_USB_SAV bit to only use bit 31.
- Change psw_read/_write to only use bit 31 for PSW_USB_AV and PSW_USB_
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 54 ++
1 file changed, 54 insertions(+)
diff --git
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create mode 100644 target-tricore
rguments.
- Remove unnecessary temp register in gen_adds/_subs.
- Add missing break in gen_compute_branch at CALL insn.
- Replace movcond with setcond at RSUB insn.
- Add AV, SAV calculation to RSUB insn.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tric
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3 files changed, 184 insertions
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- Remove gen_calc_psw_sv, gen_calc_psw_av, gen_calc_psw_sav functions.
- Replace gen_calc_psw_sv, gen_calc_psw_
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59 ++
target-tricore
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
---
configure | 5 ++
default-configs/tricore-softmmu.mak | 3 +
target-tricore/translate.c
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- Add missing break in gen_compute_branch at CALL insn.
target-tricore/helper.h|
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- Replace first movcond with tcg_gen_setcond and second with tcg_gen_or at
RSUB insn.
- Add AV, SAV calculation
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C;
+target_ulong PSW_USB_V;
+target_ulong
On 08/08/2014 11:40 AM, Bastian Koppelmann wrote:
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C
On 02/10/2015 03:18 PM, Bastian Koppelmann wrote:
Hi,
the patchset fixes two minor bugs and takes care of all the packed/fixed point
mac instructions. So far I only implemented all the multiply-add instructions,
since the multiply-sub instructions are similar and I don't want the reviewe
iewed I will send another
patchset containing all the multiply-sub instructions.
I do plan on mirroring the multiply-add instructions, which seems okay. However
if there are ideas to make this more clean, let me know.
Cheers,
Bastian
v1 -> v2:
* fix obvious style issues found by checkpatch
values in q-format
/ and saturate each result.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 3 +
target-tricore/op_helper.c | 110
target-tricore/translate.c | 421 +
3 files changed, 534
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a73b700..cfd6a77 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.
Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.
Signed-off-by: Bastian Koppelmann
---
target-tricore
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 149 +++
target-tricore/tricore-opcodes.h | 2 +-
2 files changed, 136 insertions(+), 15 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index cfd6a77
32 bit signed values does not cause an
overflow on the guest, because all intermediate results should be handled as if
they are indefinitely precise. We handle this by inverting the overflow bit for
all cases: a + (0x8000 * 0x8000) << 1.
Signed-off-by: Bastian Koppelmann
---
target-tric
both results / and
saturate each resulting word independetly.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 2 +
target-tricore/op_helper.c | 84
target-tricore/translate.c | 332 +
3 files
-target.c | 13 +++--
35 files changed, 417 insertions(+), 442 deletions(-)
Reviewed-by: Bastian Koppelmann
Nicely done. This makes me wonder, if it's worth it to remove the hard
limit for tcg temps too.
Cheers,
Bastian
On 02/11/2015 04:48 PM, Bastian Koppelmann wrote:
Hi,
the patchset fixes two minor bugs and takes care of all the packed/fixed point
mac instructions. So far I only implemented all the multiply-add instructions,
since the multiply-sub instructions are similar and I don't want the reviewe
On 02/17/2015 07:56 PM, Richard Henderson wrote:
On 02/11/2015 08:49 AM, Bastian Koppelmann wrote:
-OPC2_32_RRR2_MADD_U_32 = 0x68,
+OPC2_32_RRR2_MADD_U_64 = 0x68,
I guess this is a change to the spec, after the V1.0, 2012-05 edition that I
On 02/22/2015 01:31 PM, Chen Gang S wrote:
Chen Gang (6):
target-tilegx: Firstly add to qemu with minimized features
linux-user: tilegx: Firstly add architecture related features
linux-user: tilegx: Add target features support within qemu
linux-user: Support tilegx architecture in sy
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5108ab0..dc89bdf 100644
--- a/target-tricore/translate.c
+++ b/target
result.
* gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left
justfied from two halftwords/words values in
q-format
/ and saturate each result.
Signed-off-by: Bastian Koppelmann
---
target-tricore
n q31
format.
Also this patchset adds the remaining instructions of the , RRRW and SYS
format. Note here that I only implemented
non trap instructions, since I'm planing to do trap handling in another patch.
Cheers,
Bastian
Bastian Koppelmann (6):
target-tricore: Add instructions of
number.
* dvadj: divide-adjust the result after dvstep instructions.
* dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.
OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helpe
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- now uses 3 helper functions (gen_mul_q, gen_mul_q_16, gen_mulr_q) to
remove repetition.
- now uses 64 arithmetic instead of emulating it.
- now uses arithmetic shift, instead of normal shift + sign extend for arg
extract
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- optimize OPC2_32_RRPW_EXTR by using only two shifts, instead of four.
- OPC1_32_RRPW_DEXTR now has r1 == r2 as a special case.
target-tricore/translate.c | 70 ++
1 file changed, 70 inserti
64 arithmetic instead of emulating it.
- MUL_Q now uses arithmetic shift, instead of normal shift + sign extend
for arg
extraction.
- optimize OPC2_32_RRPW_EXTR by using only two shifts, instead of four.
- OPC1_32_RRPW_DEXTR now has r1 == r2 as a special case.
Bastian Koppelmann
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 804d181..8f9679e 100644
--- a/target-tricore/translate.c
+++ b/target-tricore
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 7382193..d5c07b2 100644
--- a/target-tricore
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 182 +
1 file changed, 182 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 57949fa..7382193 100644
--- a/target
From: Peter Maydell
Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.
Signed-off-by: Peter Maydell
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
Bastian Koppelmann (8):
target-tricore: Several translator and cpu model fixes
target-tricore: calculate av bits before saturation
target-tricore: Fix bugs found by coverity
target-tricore: split up suov32 into suov32_pos and suov32_neg
target
64 bit mac instructions calculated the av bits after the saturation, which
resulted in a wrong PSW. This moves the av bit calculation before the
saturation.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 28
1 file changed, 16 insertions(+), 12
ns for suov32 up into two functions
(suov32_pos, suov32_neg) for each case.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target-tricore/op_helper.c b/target-t
comment to avoid
the false positive in the future.
Reported-by: Markus Armbruster
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.h | 1 +
target-tricore/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 70 ++
1 file changed, 70 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d5c07b2..2cdc996 100644
--- a/target
number.
* dvadj: divide-adjust the result after dvstep instructions.
* dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.
OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helpe
Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.c | 2 +-
target-tricore/op_helper.c | 1 +
target-tricore
On 01/27/2015 10:40 AM, Peter Maydell wrote:
On 26 January 2015 at 20:03, Bastian Koppelmann
wrote:
The following changes since commit 1ac0206b2ae1ffaeec564f110664a3a77bafafd2:
qemu-timer.c: Trim list of included headers (2015-01-26 18:15:54 +)
are available in the git repository at
64 bit mac instructions calculated the av bits after the saturation, which
resulted in a wrong PSW. This moves the av bit calculation before the
saturation.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 28
1 file changed, 16 insertions(+), 12
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 70 ++
1 file changed, 70 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ea0a2fc..8943a39 100644
--- a/target
Bastian Koppelmann (8):
target-tricore: Several translator and cpu model fixes
target-tricore: calculate av bits before saturation
target-tricore: Fix bugs found by coverity
target-tricore: split up suov32 into suov32_pos and suov32_neg
target
Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.c | 2 +-
target-tricore/op_helper.c | 1 +
target-tricore
From: Peter Maydell
Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.
Signed-off-by: Peter Maydell
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5e9eb28..ea0a2fc 100644
--- a/target-tricore
number.
* dvadj: divide-adjust the result after dvstep instructions.
* dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.
OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helpe
ns for suov32 up into two functions
(suov32_pos, suov32_neg) for each case.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target-tricore/op_helper.c b/target-t
comment to avoid
the false positive in the future.
Reported-by: Markus Armbruster
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.h | 1 +
target-tricore/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 182 +
1 file changed, 182 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 57949fa..5e9eb28 100644
--- a/target
| 286 ++-
tcg/tcg-op.c | 190 ---
tcg/tcg.c | 376 +++---
tcg/tcg.h | 58 ---
5 files changed, 431 insertions(+), 501 deletions(-)
Reviewed-by: Bastian
-
tcg/tcg-op.h | 1 -
3 files changed, 35 insertions(+), 44 deletions(-)
Reviewed-by: Bastian Koppelmann
.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
Makefile.target |2 +-
tcg/tcg-op.c| 1978 +++
tcg/tcg-op.h| 2488 ---
tcg/tcg.c | 137 ---
tcg/tcg.h
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a73b700..cfd6a77 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.
Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.
Signed-off-by: Bastian Koppelmann
---
target-tricore
values in q-format
/ and saturate each result.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 3 +
target-tricore/op_helper.c | 110
target-tricore/translate.c | 421 +
3 files changed, 534
iewed I will send another
patchset containing all the multiply-sub instructions.
I do plan on mirroring the multiply-add instructions, which seems okay. However
if there are ideas to make this more clean, let me know.
Cheers,
Bastian
Bastian Koppelmann (6):
target-tricore: Fix RLC_ADDI, RLC_
both results / and
saturate each resulting word independetly.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 2 +
target-tricore/op_helper.c | 84
target-tricore/translate.c | 332 +
3 files
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 149 +++
target-tricore/tricore-opcodes.h | 2 +-
2 files changed, 136 insertions(+), 15 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index cfd6a77
32 bit signed values does not cause
an
overflow on the guest, because all intermediate results should be handled as if
they are indefinitely precise. We handle this by inverting the overflow bit for
all cases: a + ((0x8000 * 0x8000) << 1).
Signed-off-by: Bastian Koppelmann
---
ta
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is
needed
for the overflow bits, after calculating the overflow bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 29 +
1 file changed, 17 insertions(+), 12 deletions
On 03/20/2015 02:34 PM, Bastian Koppelmann wrote:
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is
needed
for the overflow bits, after calculating the overflow bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 29
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