Hi,
my aim is to add Infineon's TriCore architecture to QEMU. This series of
patches adds the target stubs, a basic testboard and a softmmu for system mode
emulation. Furthermore it adds all the 16 bit long instructions of the
architecture grouped by opcode format.
After this series of patches. Another one will follow, which adds a lot of the
32 bit long instructions.
All the best
Bastian
v2 -> v3:
- Add cache for PSW_USB bits and psw_write/_read functions.
- Add tricore_feature, set_feature functions and enum of cpu features.
- Remove translate_init.c.
- Move init code from translate_init.c to cpu.c and use type_register
instead of a custom list.
- Add cpu model aurix and tc1796, which use set_feature.
- Move tricore_cpu_list to helper.c and now uses GSList.
- Move cpu_tricore_init from translate.c to helper.c and now uses
cpu_generic_init
- Add initialization for PSW_USB bits as TCG regs.
- Remove helper_shac, gen_shac
- Remove len parameter of gen_shaci
- Change gen_shaci to a special case.
- Add gen_calc_psw_* functions to generate the calculation of PSW bits.
- Add gen_add/sub/mul_i32 micro-op generator, that handles PSW bits.
- Replace ADD/SUB/MUL instructions with gen_add/sub/mul_i32 for PSW bit
calculation.
- Change OP_COND to handle PSW bits.
- MOV_A: Remove sign extended loading of const4
- gen_shi: Remove wrong documentation
- Fix PSW bit calculation in SSOV makro.
- Fix CDC.COUNT calculation in cdc_increment/_decrement/_zero.
- helper_ret/_call now use psw_read/_write.
- helper_ret now stores PSW depending on TRICORE_FEATURE.
- helper_ret now uses psw_write.
- Add missing temp_free to gen_saturate.
- RSUB: replace tcg_gen_subfi_tl with tcg_gen_net_tl.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
target-tricore: Add instructions of SRC opcode format
target-tricore: Add instructions of SRR opcode format
target-tricore: Add instructions of SSR opcode format
target-tricore: Add instructions of SRRS and SLRO opcode format
target-tricore: Add instructions of SB opcode format
target-tricore: Add instructions of SBC and SBRN opcode format
target-tricore: Add instructions of SBR opcode format
target-tricore: Add instructions of SC opcode format
target-tricore: Add instructions of SLR, SSRO and SRO opcode format
target-tricore: Add instructions of SR opcode format
arch_init.c | 2 +
configure | 5 +
cpu-exec.c | 11 +-
cpus.c | 6 +
default-configs/tricore-softmmu.mak | 3 +
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 ++++
include/elf.h | 2 +
include/hw/tricore/tricore.h | 54 ++
include/sysemu/arch_init.h | 1 +
target-tricore/Makefile.objs | 1 +
target-tricore/cpu-qom.h | 71 ++
target-tricore/cpu.c | 191 +++++
target-tricore/cpu.h | 402 ++++++++++
target-tricore/helper.c | 144 ++++
target-tricore/helper.h | 25 +
target-tricore/op_helper.c | 388 ++++++++++
target-tricore/translate.c | 1225 ++++++++++++++++++++++++++++++
target-tricore/tricore-defs.h | 28 +
target-tricore/tricore-opcodes.h | 1406 +++++++++++++++++++++++++++++++++++
20 files changed, 4094 insertions(+), 1 deletion(-)
create mode 100644 default-configs/tricore-softmmu.mak
create mode 100644 hw/tricore/Makefile.objs
create mode 100644 hw/tricore/tricore_testboard.c
create mode 100644 include/hw/tricore/tricore.h
create mode 100644 target-tricore/Makefile.objs
create mode 100644 target-tricore/cpu-qom.h
create mode 100644 target-tricore/cpu.c
create mode 100644 target-tricore/cpu.h
create mode 100644 target-tricore/helper.c
create mode 100644 target-tricore/helper.h
create mode 100644 target-tricore/op_helper.c
create mode 100644 target-tricore/translate.c
create mode 100644 target-tricore/tricore-defs.h
create mode 100644 target-tricore/tricore-opcodes.h
--
2.0.4
