Hi,
my aim is to add Infineon's TriCore architecture to QEMU. This series of
patches adds the target stubs, a basic testboard and a softmmu for system mode
emulation. Furthermore it adds all the 16 bit long instructions of the
architecture grouped by opcode format.
After this series of patches. Another one will follow, which adds a lot of the
32 bit long instructions.
All the best
Bastian
v3 -> v4:
- tricore_cpu_type_info changed to abstract.
- Change documentation of PSW_USB_AV and PSW_USB_SAV bit to only use bit 31.
- Change psw_read/_write to only use bit 31 for PSW_USB_AV and PSW_USB_SAV.
- Remove gen_calc_psw_sv, gen_calc_psw_av, gen_calc_psw_sav functions.
- Rename gen_add_i32 to gen_add_d.
- Remove psw calculation from ADD_A.
- Replace makro OP_COND with function gen_cond_add, gen_cond_addi.
- gen_shaci now uses only 32 bit tcg shifts and implments special case of
exactly 32 bit long shift.
- gen_cond_add now sets V and AV bits conditionaly through temp registers.
- Rename gen_sub_i32 to gen_sub_d.
- Fix V bit calculation in gen_sub_d and gen_mul_i32s.
- helper_add/sub_ssov now uses sign extended arguments.
- Remove unnecessary temp register in gen_adds/_subs.
- Add missing break in gen_compute_branch at CALL insn.
- Replace movcond with setcond at RSUB insn.
- Add AV, SAV calculation to RSUB insn.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target-tricore: Add board for systemmode
target-tricore: Add softmmu support
target-tricore: Add initialization for translation and activate target
target-tricore: Add masks and opcodes for decoding
target-tricore: Add instructions of SRC opcode format
target-tricore: Add instructions of SRR opcode format
target-tricore: Add instructions of SSR opcode format
target-tricore: Add instructions of SRRS and SLRO opcode format
target-tricore: Add instructions of SB opcode format
target-tricore: Add instructions of SBC and SBRN opcode format
target-tricore: Add instructions of SBR opcode format
target-tricore: Add instructions of SC opcode format
target-tricore: Add instructions of SLR, SSRO and SRO opcode format
target-tricore: Add instructions of SR opcode format
arch_init.c | 2 +
configure | 5 +
cpu-exec.c | 11 +-
cpus.c | 6 +
default-configs/tricore-softmmu.mak | 3 +
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 ++++
include/elf.h | 2 +
include/hw/tricore/tricore.h | 54 ++
include/sysemu/arch_init.h | 1 +
target-tricore/Makefile.objs | 1 +
target-tricore/cpu-qom.h | 71 ++
target-tricore/cpu.c | 191 +++++
target-tricore/cpu.h | 401 ++++++++++
target-tricore/helper.c | 144 ++++
target-tricore/helper.h | 25 +
target-tricore/op_helper.c | 392 ++++++++++
target-tricore/translate.c | 1222 ++++++++++++++++++++++++++++++
target-tricore/tricore-defs.h | 28 +
target-tricore/tricore-opcodes.h | 1406 +++++++++++++++++++++++++++++++++++
20 files changed, 4094 insertions(+), 1 deletion(-)
create mode 100644 default-configs/tricore-softmmu.mak
create mode 100644 hw/tricore/Makefile.objs
create mode 100644 hw/tricore/tricore_testboard.c
create mode 100644 include/hw/tricore/tricore.h
create mode 100644 target-tricore/Makefile.objs
create mode 100644 target-tricore/cpu-qom.h
create mode 100644 target-tricore/cpu.c
create mode 100644 target-tricore/cpu.h
create mode 100644 target-tricore/helper.c
create mode 100644 target-tricore/helper.h
create mode 100644 target-tricore/op_helper.c
create mode 100644 target-tricore/translate.c
create mode 100644 target-tricore/tricore-defs.h
create mode 100644 target-tricore/tricore-opcodes.h
--
2.0.4
