The following changes since commit 1ac0206b2ae1ffaeec564f110664a3a77bafafd2:
qemu-timer.c: Trim list of included headers (2015-01-26 18:15:54 +0000) are available in the git repository at: https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150127 for you to fetch changes up to 0953225588ee30de2e92485331ad1bb3d7c7d089: target-tricore: Add instructions of RRR opcode format (2015-01-27 11:48:02 +0000) ---------------------------------------------------------------- tricore bugfixes and RR1, RR2, RRPW and RRR insn ---------------------------------------------------------------- Bastian Koppelmann (8): target-tricore: Several translator and cpu model fixes target-tricore: calculate av bits before saturation target-tricore: Fix bugs found by coverity target-tricore: split up suov32 into suov32_pos and suov32_neg target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode target-tricore: Add instructions of RR2 opcode format target-tricore: Add instructions of RRPW opcode format target-tricore: Add instructions of RRR opcode format Peter Maydell (1): target-tricore: Add missing ULL suffix on 64 bit constant target-tricore/cpu.c | 2 +- target-tricore/cpu.h | 1 + target-tricore/helper.h | 8 + target-tricore/op_helper.c | 232 +++++++++++++++++--- target-tricore/translate.c | 448 ++++++++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 2 +- 6 files changed, 659 insertions(+), 34 deletions(-) -- 2.2.2
