Re: [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

On Wed, Dec 15, 2021 at 6:38 AM Kip Walker wrote: > > On Fri, Dec 10, 2021 at 8:35 PM Anup Patel wrote: > > > > We should use the AIA INTC compatible string in the CPU INTC > > DT nodes when the CPUs support AIA feature. This will allow > > Linux INTC driver t

Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)

On Fri, Jul 14, 2023 at 3:43 AM Conor Dooley wrote: > > +CC OpenSBI Mailing list > > I've not yet had the chance to bisect this, so adding the OpenSBI folks > to CC in case they might have an idea for what to try. > > And a question for you below Daniel. > > On Wed, Jul 12, 2023 at 11:14:21PM +010

Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)

On Fri, Jul 14, 2023 at 3:50 PM Conor Dooley wrote: > > On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote: > > > &

Re: Is it possible to boot a riscv32 guest on riscv64 host using KVM?

On Mon, Jun 26, 2023 at 4:57 PM Philippe Mathieu-Daudé wrote: > > Hi, > > I'm working on a tree-wide accelerator refactor and want > to run various configs to be sure I didn't broke anything. > > QEMU theoretically supports running a riscv32 guest using > KVM on a riscv64 host, however the documen

Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.

d `mmsiaddrcfgh`. > > Signed-off-by: Tommy Wu > Reviewed-by: Frank Chang Looks good to me. Reviewed-by: Anup Patel > --- > hw/intc/riscv_aplic.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.

Re: [PATCH v5 0/3] hw/riscv/virt: pflash improvements

On Fri, May 26, 2023 at 5:41 PM Sunil V L wrote: > > This series improves the pflash usage in RISC-V virt machine with solutions to > below issues. > > 1) Currently the first pflash is reserved for ROM/M-mode firmware code. But > S-mode > payload firmware like EDK2 need both pflash devices to hav

Re: [PATCH] hw/riscv: split RAM into low and high memory

On Tue, Aug 1, 2023 at 4:16 AM Daniel Henrique Barboza wrote: > > > > On 7/30/23 22:53, Fei Wu wrote: > > riscv virt platform's memory started at 0x8000 and > > straddled the 4GiB boundary. Curiously enough, this choice > > of a memory layout will prevent from launching a VM with > > a bit mor

Re: [PATCH] hw/riscv: split RAM into low and high memory

AM].size) { > > > +fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > > > memmap[VIRT_DRAM].size, > > > machine); > > > +} else { > > > +

Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency

On Thu, Dec 16, 2021 at 10:31 AM Alistair Francis wrote: > > From: Alistair Francis > > As per the device tree specification let's set the clock-frequency for > the virt CPUs. > > QEMU doesn't really have an exact clock, so let's just 100 as it's a > nice round number and matches the sifive_u

Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default

the virt machine. > > Signed-off-by: Alistair Francis Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1edb2771b4..

Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores

64. IMO, we should keep QEMU VIRT_CPUS_MAX as high as possible to allow any kind of software Linux, OpenSBI, FreeBSD, Xvisor, Xen, etc. Let the guest software decide it's own limit (such as NR_CPUS of Linux). Reviewed-by: Anup Patel Regards, Anup > --- > include/hw/riscv/virt.h | 2

Re: [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental

On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis wrote: > > From: Alistair Francis > > The Hypervisor spec is now frozen, so remove the experimental tag. > > Signed-off-by: Alistair Francis Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > target

Re: [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

On Tue, Dec 21, 2021 at 12:18 PM Alistair Francis wrote: > > On Sat, Dec 11, 2021 at 2:34 PM Anup Patel wrote: > > > > The AIA specification introduces new [m|s|vs]topi CSRs for > > reporting pending local IRQ number and associated IRQ priority. > >

Re: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM

On Mon, Dec 20, 2021 at 6:39 PM Yifei Jiang wrote: > > Get kernel and fdt start address in virt.c, and pass them to KVM > when cpu reset. Add kvm_riscv.h to place riscv specific interface. > > In addition, PLIC is created without M-mode PLIC contexts when KVM > is enabled. > > Signed-off-by: Yifei

Re: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM

On Thu, Dec 23, 2021 at 11:33 AM Anup Patel wrote: > > On Mon, Dec 20, 2021 at 6:39 PM Yifei Jiang wrote: > > > > Get kernel and fdt start address in virt.c, and pass them to KVM > > when cpu reset. Add kvm_riscv.h to place riscv specific interface. > > > > In

Re: [PATCH v3 07/12] target/riscv: Support setting external interrupt by KVM

On Mon, Dec 20, 2021 at 6:39 PM Yifei Jiang wrote: > > When KVM is enabled, set the S-mode external interrupt through > kvm_riscv_set_irq function. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis Looks good to me. Reviewed-by:

Re: [PATCH v3 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

t doesn't matter > that adaping in QEMU. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > target/riscv/cpu.h | 7 + > target/riscv/kvm.c | 72 +++

[PATCH v6 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia

[PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Review

[PATCH v6 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by

[PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by

[PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c

[PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c

[PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 + target

[PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c | 156 + 1 file changed, 156

[PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish

[PATCH v6 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 127

[PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv

[PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c

[PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example

[PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10

[PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v6 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

[PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any

[PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- ta

[PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c

[PATCH v6 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v6 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- docs/system/riscv/virt.rst | 16

[PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level

[PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by

[PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h

Re: [PATCH v2 2/3] target/riscv: add support for svinval extension

On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li wrote: > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 7 ++ > target/riscv/in

Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension

On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote: > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cpu.c| 1 + > target/riscv/cpu.h| 1 + > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_helper.c | 20 > 4 files changed

Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension

On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote: > > It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is > sequentially consistent and doesn't model PMAs currently > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > --- > target/riscv

Re: [PATCH for 5.0 v1 0/2] RISC-V: Fix Hypervisor guest user space

; Thanks, these are in the queue. > I have tested this patch series on latest QEMU master without "target/riscv: Don't set write permissions on dirty PTEs" workaround patch. It works fine now. Tested-by: Anup Patel Please drop the work-around patch "target/riscv: Don't set write permissions on dirty PTEs" from your for-next. Regards, Anup

[PATCH] riscv: Fix Stage2 SV32 page table walk

able. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 50e13a064f..bc80aa87cf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -559,

Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang wrote: > > Use char-fe handler console sbi call, which implement early > console io while apply 'earlycon=sbi' into kernel parameters. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/kvm.c | 54 +

Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang wrote: > > Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. > Meanwhile, add riscv64 kvm support to configure. This should be for both riscv64 and riscv32. The KVMTOOL compiles perfectly fine for riscv32 (although not tested

Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

On Tue, Mar 31, 2020 at 2:56 PM Jiangyifei wrote: > > > > -Original Message- > > From: Anup Patel [mailto:a...@brainfault.org] > > Sent: Tuesday, March 31, 2020 1:17 PM > > To: Jiangyifei > > Cc: QEMU Developers ; open list:RISC-V > ri...@

Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

On Tue, Mar 31, 2020 at 2:43 PM Anup Patel wrote: > > On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang wrote: > > > > Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. > > Meanwhile, add riscv64 kvm support to configure. > > This should be for

[PATCH v2 0/3] RISC-V Spike machine improvements

This series improves QEMU Spike machine to: 1. Allow loading OpenBI firmware using -bios option 2. Allow more than one CPUs Changes since v1: - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0) Anup Patel (3): hw/riscv: Add optional symbol callback ptr to

[PATCH v2 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option

This patch extends Spike machine support to allow loading OpenSBI firmware (fw_jump.elf) separately using -bios option. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c

[PATCH v2 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()

mbols from firmware ELF passed via "-bios" option. Signed-off-by: Anup Patel --- hw/riscv/boot.c | 13 - hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 6 -- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/

[PATCH v2 3/3] hw/riscv/spike: Allow more than one CPUs

Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 2 +- 1 file

Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

On Fri, Aug 14, 2020 at 10:12 PM Bin Meng wrote: > > From: Bin Meng > > This adds support for Microchip PolarFire SoC Icicle Kit board. > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's > E51 plus four U54 cores and many on-chip peripherals and an FPGA. Nice Work !!! This is v

Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

> >> > >> On 8/17/20 11:30 AM, Bin Meng wrote: > >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >>> the content is safe > >>> > >>> Hi Anup, > >>> > >>> On Sat, Aug 15, 2020 at 1:44

Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

On Tue, Aug 18, 2020 at 6:39 PM wrote: > > On 8/18/20 7:17 AM, Anup Patel wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > On Tue, Aug 18, 2020 at 1:23 AM wrote: > >> On 8/17/20 8:28 PM,

Re: [PATCH RFC 0/9] Add riscv64 kvm accel support

g out KVM RISC-V v11 series today. There is a crucial bug fix related to HIDELEG CSR programing. This bug fix is required in both QEMU and KVM RISC-V. Palmer has already accepted QEMU HIDELEG CSR fix. The KVM RISC-V v11 series will have this fix as well. Thanks & Regards, Anup Patel

[PATCH v3 0/3] RISC-V Spike machine improvements

This series improves QEMU Spike machine to: 1. Allow loading OpenBI firmware using -bios option 2. Allow more than one CPUs Changes since v2: - Rebased on QEMU v5.0-rc4 Changes since v1: - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0) Anup Patel (3): hw/riscv: Add

[PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option

This patch extends Spike machine support to allow loading OpenSBI firmware (fw_jump.elf) separately using -bios option. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c

[PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs

Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 2 +- 1 file

[PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()

mbols from firmware ELF passed via "-bios" option. Signed-off-by: Anup Patel --- hw/riscv/boot.c | 13 - hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 6 -- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/

Re: [PATCH] riscv/spike: Change the default bios to use plain binary image

On Fri, May 1, 2020 at 6:01 PM Bin Meng wrote: > > From: Bin Meng > > To keep sync with other RISC-V machines, change the default bios > to use .bin instead of the .elf images. > > Signed-off-by: Bin Meng > --- > > hw/riscv/spike.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > >

RE: [PATCH] riscv/spike: Change the default bios to use plain binary image

> -Original Message- > From: Qemu-riscv bounces+anup.patel=wdc@nongnu.org> On Behalf Of Bin Meng > Sent: 01 May 2020 18:15 > To: Anup Patel > Cc: Bin Meng ; open list:RISC-V ri...@nongnu.org>; Sagar Karandikar ; Bastian > Koppelmann ; Palmer Dabbelt

Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform

ROSS_COMPILE=$(riscv64_cross_prefix) \ > - PLATFORM="sifive/fu540" > - cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin > ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin > + PLATFORM="generic" > + cp opensbi/build/platform/generic/firmware/fw_jump.bin > ../pc-bios/opensbi-riscv64-generic-fw_jump.bin Same as above. > > bios-microvm: > $(MAKE) -C qboot > diff --git a/roms/opensbi b/roms/opensbi > index 9f1b72c..4f18c6e 16 > --- a/roms/opensbi > +++ b/roms/opensbi > @@ -1 +1 @@ > -Subproject commit 9f1b72ce66d659e91013b358939e832fb27223f5 > +Subproject commit 4f18c6e55049d858c62e87d2605dd41c06956e4e > -- > 2.7.4 > > Otherwise looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH 2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform

ke -j${JOBS} -C roms opensbi32-sifive_u 2>&1 > 1>opensbi32-sifive_u-stdout.log | tee -a opensbi32-sifive_u-stderr.log >&2 > - - make -j${JOBS} -C roms/opensbi clean > - - make -j${JOBS} -C roms opensbi64-sifive_u 2>&1 > 1>opensbi64-sifive_u-stdout.log | tee -a opensbi64-sifive_u-stderr.log >&2 > + - make -j${JOBS} -C roms opensbi64-generic 2>&1 > 1>opensbi64-generic-stdout.log | tee -a opensbi64-generic-stderr.log >&2 > -- > 2.7.4 > > Otherwise looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH 4/5] riscv/spike: Change the default bios to use generic platform image

ed(TARGET_RISCV32) > -# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" > +# define BIOS_FILENAME "opensbi-riscv32-generic-fw_jump.elf" > #else > -# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf" > +# define BIOS_FILENAME "open

Re: [PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u

diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin > b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin > deleted file mode 100644 > index 1acee86..000 > Binary files a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin and /dev/null > differ > diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin > b/pc-bios/opensbi-riscv64-virt-fw_jump.bin > deleted file mode 100644 > index c62f2b4..000 > Binary files a/pc-bios/opensbi-riscv64-virt-fw_jump.bin and /dev/null differ > -- > 2.7.4 > > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH 5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

* running QEMU test will complain hence let's suppress the error > + * report for QEMU testing. > + */ > +error_report("Unable to load the RISC-V firmware \"%s\"", > + firmware_filename); > +exit(1); > +} > } > > return filename; > -- > 2.7.4 > > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform

On Mon, May 4, 2020 at 12:46 PM Bin Meng wrote: > > Hi Anup, > > On Sun, May 3, 2020 at 12:38 PM Anup Patel wrote: > > > > On Fri, May 1, 2020 at 9:26 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > The RISC-V generic pl

Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform

On Mon, May 4, 2020 at 1:35 PM Bin Meng wrote: > > On Mon, May 4, 2020 at 4:00 PM Bin Meng wrote: > > > > Hi Anup, > > > > On Mon, May 4, 2020 at 3:52 PM Anup Patel wrote: > > > > > > On Mon, May 4, 2020 at 12:46 PM Bin Meng wrote: > > &g

Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

On Sat, Jun 20, 2020 at 2:44 AM Alistair Francis wrote: > > On Wed, Jun 17, 2020 at 8:48 PM Anup Patel wrote: > > > > On Thu, Jun 18, 2020 at 7:15 AM Alistair Francis > > wrote: > > > > > > On Mon, Jun 15, 2020 at 8:24 PM Anup Patel wrote: > &

RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images

> -Original Message- > From: Qemu-riscv bounces+anup.patel=wdc@nongnu.org> On Behalf Of Bin Meng > Sent: 22 June 2020 12:03 > To: Alistair Francis ; Bastian Koppelmann > ; Palmer Dabbelt > ; Sagar Karandikar > ; qemu-devel@nongnu.org; qemu- > ri...@nongnu

RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images

> -Original Message- > From: Bin Meng > Sent: 22 June 2020 17:43 > To: Anup Patel > Cc: Alistair Francis ; Bastian Koppelmann > ; Palmer Dabbelt > ; Sagar Karandikar > ; qemu-devel@nongnu.org; qemu- > ri...@nongnu.org; Anup Patel ; Bin Meng > >

RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images

> -Original Message- > From: Bin Meng > Sent: 22 June 2020 17:57 > To: Anup Patel > Cc: Alistair Francis ; Bastian Koppelmann > ; Palmer Dabbelt > ; Sagar Karandikar > ; qemu-devel@nongnu.org; qemu- > ri...@nongnu.org; Anup Patel ; Bin Meng > >

[PATCH 0/3] Trapped instruction encoding support

instruction is available in MTINST/HTINST CSR. This series implements optional RISC-V HART feature to provide trapped instruction encoding in appropriate CSR. These patches can be found in riscv_trap_insn_v1, branch at: https://github.com/avpatel/qemu.git Anup Patel (3): target/riscv: Optional feature

[PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs

provides original trapped instruction opcode in MTVAL/STVAL CSRs for illegal/virtual instruction trap. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 7 +++ target/riscv/cpu.h| 11 ++- target/riscv/cpu_helper.c | 6 ++ target/riscv/translate.c | 14

[PATCH 2/3] target/riscv: Fix write_htinst() implementation

The htinst CSR is writeable from M-mode and HS-mode so we should not ignore writes to htinst CSR. Signed-off-by: Anup Patel --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f985b85de4..99fcb7f67d 100644 --- a/target/riscv

[PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt()

When RISCV_FEATURE_TINST feature is enabled, we should write transformed instruction encoding of the trapped instruction in MTINST/HTINST CSR at time of taking trap. We update riscv_cpu_do_interrupt() as-per above. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 166

RE: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

> -Original Message- > From: Alistair Francis > Sent: 26 June 2020 00:20 > To: Anup Patel > Cc: Anup Patel ; Peter Maydell > ; Palmer Dabbelt ; > Alistair Francis ; Sagar Karandikar > ; Atish Patra ; open > list:RISC-V ; qemu-devel@nongnu.org > Developers

[PATCH 0/2] RTC support for QEMU RISC-V virt machine

it in Kconfig for RISCV and also update Linux defconfigs. We have tested this series with Linux-5.3 plus defconfig changes available in 'goldfish_rtc_v1' branch of: https://github.com/avpatel/linux.git Anup Patel (2): hw: timer: Add Goldfish RTC device riscv: virt: Use Goldfish RTC de

[PATCH 2/2] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 15 +++ include/hw/

[PATCH 1/2] hw: timer: Add Goldfish RTC device

migration support is not available for Goldfish RTC device but it will be added later when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel --- hw/timer/Kconfig| 3 + hw/timer/Makefile.objs | 1 + hw/timer/goldfish_rtc.c | 221

RE: [PATCH 1/2] hw: timer: Add Goldfish RTC device

> -Original Message- > From: Peter Maydell > Sent: Tuesday, September 24, 2019 3:21 PM > To: Anup Patel > Cc: Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Bastian Koppelmann ; Atish Patra > ; qemu-ri...@nongnu.org; qemu- > de...@nongnu.org

RE: [PATCH 1/2] hw: timer: Add Goldfish RTC device

> -Original Message- > From: Peter Maydell > Sent: Tuesday, September 24, 2019 5:02 PM > To: Anup Patel > Cc: Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Bastian Koppelmann ; Atish Patra > ; qemu-ri...@nongnu.org; qemu- > de...@nongnu.org

[PATCH v2 0/2] RTC support for QEMU RISC-V virt machine

- Added vmstate for Goldfish RTC Anup Patel (2): hw: timer: Add Goldfish RTC device riscv: virt: Use Goldfish RTC device hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 15 ++ hw/timer/Kconfig| 3 + hw/timer/Makefile.objs | 1 + hw/timer

[PATCH v2 1/2] hw: timer: Add Goldfish RTC device

migration support is not available for Goldfish RTC device but it will be added later when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel --- hw/timer/Kconfig| 3 + hw/timer/Makefile.objs | 1 + hw/timer/goldfish_rtc.c | 278

[PATCH v2 2/2] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 15 +++ include/hw/

RE: [PATCH v2 0/2] RTC support for QEMU RISC-V virt machine

> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Tuesday, September 24, 2019 7:35 PM > To: Anup Patel ; Peter Maydell > ; Palmer Dabbelt ; Alistair > Francis ; Sagar Karandikar > ; Bastian Koppelmann paderborn.de> > Cc: Atish Patra ; qemu-r

RE: [PATCH 0/2] RTC support for QEMU RISC-V virt machine

> -Original Message- > From: Richard W.M. Jones > Sent: Friday, September 27, 2019 6:01 PM > To: Anup Patel > Cc: Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Bastian Koppelmann ; Atish Patra > ; qemu-ri...@nongnu.org; qemu- > de...@nongnu.org

RE: [PATCH 0/2] RTC support for QEMU RISC-V virt machine

> -Original Message- > From: Richard W.M. Jones > Sent: Friday, September 27, 2019 5:21 PM > To: Anup Patel > Cc: Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Bastian Koppelmann ; Atish Patra > ; qemu-ri...@nongnu.org; qemu- > de...@nongnu.org

[PATCH 0/2] RISC-V TIME CSR for privileged mode

-v0.5.1 branch of https://github.com/kvm-riscv/qemu.git and can be found in riscv_time_csr_v1 branch of same repo. Anup Patel (2): target/riscv: Emulate TIME CSRs for privileged mode hw/riscv: Provide rdtime callback for TCG in CLINT emulation hw/riscv/sifive_clint.c | 1 + target/riscv/cpu.h

[PATCH 1/2] target/riscv: Emulate TIME CSRs for privileged mode

not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 5 +++ target/riscv/cpu_helper.c | 5 +++ target

[PATCH 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

This patch extends CLINT emulation to provide rdtime callback for TCG. This rdtime callback will be called wheneven TIME CSRs are read in privileged modes. Signed-off-by: Anup Patel --- hw/riscv/sifive_clint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/sifive_clint.c b/hw

Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

On Tue, Jan 21, 2020 at 4:43 PM Alistair Francis wrote: > > On Wed, Jan 8, 2020 at 12:07 PM Palmer Dabbelt > wrote: > > > > On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote: > > > Signed-off-by: Alistair Francis > > > --- > > > target/riscv/csr.c | 3 +++ > > > 1 file changed,

[PATCH v2 0/2] RISC-V TIME CSR for privileged mode

-v0.5.1 branch of https://github.com/kvm-riscv/qemu.git and can be found in riscv_time_csr_v2 branch of same repo. Changes since v1: - Use braces for single-line if-statements Anup Patel (2): target/riscv: Emulate TIME CSRs for privileged mode hw/riscv: Provide rdtime callback for TCG in CLINT

[PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode

not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 5 +++ target/riscv

[PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

This patch extends CLINT emulation to provide rdtime callback for TCG. This rdtime callback will be called wheneven TIME CSRs are read in privileged modes. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/sifive_clint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw

Re: [PATCH v8 0/3] RTC support for QEMU RISC-V virt machine

On Thu, Nov 7, 2019 at 10:22 PM Palmer Dabbelt wrote: > > On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote: > > This series adds RTC device to QEMU RISC-V virt machine. We have > > selected Goldfish RTC device model for this. It's a pretty simple > > s

[PATCH v2] riscv/virt: Add syscon reboot and poweroff DT nodes

The SiFive test device found on virt machine can be used by generic syscon reboot and poweroff drivers available in Linux kernel. This patch updates FDT generation in virt machine so that Linux kernel can probe and use generic syscon drivers. Signed-off-by: Anup Patel --- Changes since v1

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