On Tue, Jan 21, 2020 at 4:43 PM Alistair Francis <alistai...@gmail.com> wrote: > > On Wed, Jan 8, 2020 at 12:07 PM Palmer Dabbelt <palmerdabb...@google.com> > wrote: > > > > On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote: > > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > > > --- > > > target/riscv/csr.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > > index a4b598d49a..fc38c45a7e 100644 > > > --- a/target/riscv/csr.c > > > +++ b/target/riscv/csr.c > > > @@ -449,6 +449,9 @@ static int read_mideleg(CPURISCVState *env, int > > > csrno, target_ulong *val) > > > static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) > > > { > > > env->mideleg = (env->mideleg & ~delegable_ints) | (val & > > > delegable_ints); > > > + if (riscv_has_ext(env, RVH)) { > > > + env->mideleg |= VS_MODE_INTERRUPTS; > > > + } > > > return 0; > > > } > > > > Do you have any idea why? The spec is explicit that this is the case, but > > I'm > > surprised. > > I'm not sure why, maybe to simplfy hardware design?
As-per my understanding, the VS-mode interrupts can be taken only when V=1 and these are injected by HS-mode using HIP CSR. If we allow VS-mode interrupts to be taken in M-mode then it means HS-mode can now inject interrupts for M-mode using HIP CSR. This cannot be allowed hence VS-mode interrupts are force delegated to S-mode in MIDELEG. Regards, Anup