n settings. One
of these settings is the endianness a guest takes its exceptions in.
Signed-off-by: Anton Blanchard
---
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 16bfab9..de639f6 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -262,7 +262,7 @@ static void *spapr_create_fdt_s
The last 8 bytes of the buffer list is defined to contain the number
of dropped frames. At the moment we use it to store rx entries,
which trips up ethtool -S:
rx_no_buffer: 9223380832981355136
Fix this by skipping the last buffer list entry.
Signed-off-by: Anton Blanchard
---
diff --git a/hw
Scubbing our ppc64 bugs. Thanks for the update Ken, I'll close this.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/965327
Title:
virtio-pci: can't reserve io 0x-0x001f
Status in QEMU:
New
B
This patchset adds support for 64bit PowerPC little endian on POWER7.
Linux kernel patches to support this were sent out earlier today:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-August/109849.html
Anton
--
Anton Blanchard (4):
target-ppc: POWER7 supports the MSR_LE bit
target
From: Benjamin Herrenschmidt
Try loading the kernel as little endian if it fails big endian.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Anton Blanchard
---
hw/ppc/spapr.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc
Add MSR_LE to the msr_mask for POWER7.
Signed-off-by: Anton Blanchard
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b14aec8..33914bc 100644
--- a/target-ppc/translate_init.c
H_SET_MODE is used for controlling various partition settings. One
of these settings is the endianness a guest takes its exceptions in.
Signed-off-by: Anton Blanchard
---
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_hcall.c | 44
include/hw/ppc
On POWER7, LPCR_ILE is used to control what endian guests take
their exceptions in so use it instead of MSR_ILE.
Signed-off-by: Anton Blanchard
---
target-ppc/cpu.h | 2 ++
target-ppc/excp_helper.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target-ppc/cpu.h b
Use info->endian to select the endian of the instruction to
be disassembled.
Signed-off-by: Anton Blanchard
---
disas/ppc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index c149506..99c4cbc 100644
--- a/disas/ppc.c
+++ b/disas/pp
Hi,
> > The distinction is important in QEMU. ppc64 is still
> > TARGET_WORDS_BIGENDIAN. We still want most stl_phys to treat
> > integers as big endian. There's just this extra concept that CPU
> > loads/stores are sometimes byte swapped. That affects virtio but
> > not a lot else.
>
> You'
signal back to the qemu-char layer that we are
ready for more input. Without this we block until something
else kicks us (eg network activity).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
Index: b/hw/char/spapr_vty.c
earlier patch. Remove the hypervisor
property.
Signed-off-by: Anton Blanchard
---
Index: b/hw/ppc/spapr.c
===
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -362,10 +362,6 @@ static void *spapr_create_fdt_skel(hwadd
_FDT((fdt_
POWER8 supports isel, so enable it in QEMU.
Signed-off-by: Anton Blanchard
Signed-off-by: Cédric Le Goater
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a82c8f9..4fda0fd 100644
Remove MSR_POW from the msr_mask for POWER7/7+/8.
Signed-off-by: Anton Blanchard
Signed-off-by: Cédric Le Goater
---
target-ppc/translate_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 87c00a1
Add MSR_LE to the msr_mask for POWER8.
Signed-off-by: Anton Blanchard
Signed-off-by: Cédric Le Goater
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7f53c33..a82c8f9 100644
Most of the PMU SPRs were wrong on Book3S.
Signed-off-by: Anton Blanchard
---
target-ppc/cpu.h| 29 -
target-ppc/translate_init.c | 139 +++-
2 files changed, 153 insertions(+), 15 deletions(-)
diff --git a/target-ppc/cpu.h b/target
Without MSR_VSX we die early during a Linux boot.
Signed-off-by: Anton Blanchard
Signed-off-by: Cédric Le Goater
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4fda0fd..87c00a1
970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
it 3 times, and simplify the existing code.
Signed-off-by: Anton Blanchard
---
target-ppc/translate_init.c | 89 -
1 file changed, 39 insertions(+), 50 deletions(-)
diff --git a/target-ppc
Hi Tom,
> This patch series addresses bugs in the recently added VSX
> instructions. Two general defects are fixed:
Thanks! This series fixes the issue I had with wget.
Tested-by: Anton Blanchard
Anton
The DAR and DSISR can be very useful when debugging issues, so add
them to ppc_cpu_dump_state. We had another bug in this area: all
of the v2.06 MMU types were missing.
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
0710
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4005,19 +4005,19 @@ static inline void gen_op_mfspr(DisasCon
* allowing
Recent Linux kernels save and restore the PPR across exceptions
so we need to handle it.
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target-ppc
-off-by: Anton Blanchard
---
Index: b/target-ppc/cpu.h
===
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -549,6 +549,8 @@ enum {
POWERPC_FLAG_BUS_CLK = 0x0002,
/* Has CFAR
From: Tom Musta
This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.
The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.
Signed-off-by: Tom Musta
Signed-off-by: Anton
From: Tom Musta
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -51,6 +51,7 @@ static
From: Tom Musta
This patch adds the lxvd2x instruction.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6
: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7039,10 +7039,28 @@ static void gen_stxvd2x(DisasContext *ct
tcg_temp_free(EA);
}
+static void gen_xxpermdi
From: Tom Musta
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7023,6
Since an OS can set LPCR_ILE we must clear it during reset. Otherwise
if we reset into an OS with a different endian we die when we take
the first exception.
This fixes an issue seen on both full emulation and KVM.
Signed-off-by: Anton Blanchard
---
diff --git a/hw/ppc/spapr.c b/hw/ppc
Add MSR_LE to the msr_mask for POWER8.
Signed-off-by: Anton Blanchard
---
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3eafbb0..7661543 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7173,7 +7173,7 @@ POWERPC_FAMILY(POWER8
POWER8 supports isel, so enable it in QEMU.
Signed-off-by: Anton Blanchard
---
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3eafbb0..7661543 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7156,7 +7156,7 @@ POWERPC_FAMILY(POWER8
Without MSR_VSX we die early during a Linux boot.
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7117,7 +7117,7 @@ POWERPC_FAMILY
Remove MSR_POW from the msr_mask for POWER7/7+/8.
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate_init.c
===
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7074,7 +7074,7 @@ POWERPC_FAMILY
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard
---
configure | 6 +++---
gdb-xml/power-vsx.xml | 44
target-ppc/translate_init.c | 22 ++
3 files changed, 69
Hi Alex,
> On 24.03.15 09:59, Anton Blanchard wrote:
> > Add the XML and functions to get and set VSX registers.
>
> Awesome, thanks. Have you verified that this works for LE as well as
> BE guests?
Unfortunately all our XML gdbstub routines have endian issues (FPU,
Altivec an
Initialise our maximum page size capability to 64kB and increase
the page_size variable from 16 to 32 bits.
Signed-off-by: Anton Blanchard
--
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 1327658..aa1ed98 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -811,6 +811,7 @@ static int
: Anton Blanchard
---
linux-user/main.c| 2 +-
target-ppc/excp_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index c855bcc..9100130 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1650,7 +1650,7 @@ void
Hi,
qemu is currently broken on ppc64. After applying the following patches
I am able to boot a ppc64 and x86-64 image successfully.
Anton
add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
sub2 has similar issues, I haven't fixed it beca
rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
Index: b/tcg/ppc64/tcg-target.c
===
---
If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 0fcf2b5..64fb0af 100644
--- a
The rldcl instruction doesn't have an sh field, so the minor opcode
of 8 is actually 4 when using the XO30 macro.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
Index: b/tcg/ppc64/tcg-target.c
===
--- a/tcg/
or opcode 2 bits.
Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Anton Blanchard
---
Index: b/tcg/ppc64/tcg-target.c
===
--- a/tcg/ppc64/tcg-target.c
+++ b/tc
From: Benjamin Herrenschmidt
Try loading the kernel as little endian if it fails big endian.
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Anton Blanchard
---
Index: b/hw/ppc/spapr.c
===
--- a/hw/ppc/spapr.c
+++ b
$dar
(qemu) print $dsisr
Signed-off-by: Tom Musta
Reviewed-by: Anton Blanchard
---
Index: b/monitor.c
===
--- a/monitor.c
+++ b/monitor.c
@@ -3186,6 +3186,9 @@ static const MonitorDef monitor_defs[] =
{ "srr0"
hen
VRT[8*eb:8*eb+15] <-- MEM(EA,2)
else
VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)
This patch adds the element inversion, as described in the last line
of the RTL.
Signed-off-by: Tom Musta
Reviewed-by: Anton Blanchard
---
Index: b/target-ppc/mem
Hi Alexey,
> > I can't get an Ubuntu Wily guest to boot on an Ubuntu Wily host in
> > PR KVM mode. The kernel in both cases is 4.2. To reproduce:
> >
> > wget -N
> > https://cloud-images.ubuntu.com/wily/current/wily-server-cloudimg-ppc64el-disk1.img
> >
> > qemu-system-ppc64 -cpu POWER8 -enable-k
We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
Signed-off-by: Anton Blanchard
---
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e7be21e..538bd87 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -696,6 +696,12 @@ static void spapr_popul
the user CPU feature bits.
Without this patch userspace processes will think they can execute
TM instructions and get killed when they try.
Signed-off-by: Anton Blanchard
Cc: sta...@vger.kernel.org
---
Michael I've added stable here because I'm seeing this on a number
of distros and wou
MMU-related features")
Signed-off-by: Anton Blanchard
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 7030b03..9a3a7c6 100644
--- a/arch/powerpc/kernel/pr
scan_features() updates cpu_user_features but not cpu_user_features2.
Amongst other things, cpu_user_features2 contains the user TM feature
bits which we must keep in sync with the kernel TM feature bit.
Signed-off-by: Anton Blanchard
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c
instructions and it dies trying.
This (together with a QEMU patch) fixes PR KVM, which doesn't currently
support TM.
Signed-off-by: Anton Blanchard
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/po
We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
Signed-off-by: Anton Blanchard
---
v2: Fix build with CONFIG_KVM disabled, noticed by Alex.
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b69995e..dc3e3c9 100644
--- a/hw/ppc/spapr.c
+++ b/hw/p
From: Anton Blanchard
We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so
add the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Anton Blanchard
---
diff --git a/include/elf.h b/include/elf.h
index 28d448b..8533b2a 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -477,6 +477,19
From: Anton Blanchard
There are a few issues with our handling of the ibm,pa-features
TM bit:
- We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
- In full emulation we have a minimal implementation of TM that always
fails, so for performance re
Hi,
> From: Richard Henderson
>
> A 32-bit rotate insn is more common on hosts than a deposit insn,
> and if the host has neither the result is truely horrific.
>
> At the same time, tidy up the temporaries within these functions,
> drop the over-use of "likely", drop some checks for identity t
Hi rth,
> > Bother. I've tentatively put a revert into ppc-for-2.7. Richard,
> > do you have a better idea how to fix it?
>
> Please try the following.
Thanks! This passes my tests. Feel free to add:
Tested-by: Anton Blanchard
Anton
Hi,
> > > Bother. I've tentatively put a revert into ppc-for-2.7. Richard,
> > > do you have a better idea how to fix it?
> >
> > Please try the following.
>
> Thanks! This passes my tests. Feel free to add:
>
> Tested-by: Anton Bl
Hi rth,
> In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
> considering the effect of a mask value that wraps around to
> the high bits of the word.
Thanks, that passes my tests.
Tested-by: Anton Blanchard
Anton
> Signed-off-by: Richard Henderson
> ---
> targ
Fix a typo in xvxsigdp where we put both results into the lower
doubleword.
Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Fix a typo in xxbrq and xxbrw where we put both results into the lower
doubleword.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file
xxspltib raises a VMX or a VSX exception depending on the register
set it is operating on. We had a check, but it was backwards.
Fixes: f113283525a4 ("target-ppc: add xxspltib instruction")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 9 +
1 file
We were using set_cpu_vsr* when we should have used set_cpu_vsrl*
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file changed, 2 insert
We should only look at 5 bits of each byte, not 6.
Fixes: 3e00884f4e9f ("target-ppc: add vrldnmi and vrlwmi instructions")
Signed-off-by: Anton Blanchard
---
target/ppc/int_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/ppc/int_
During the conversion these instructions were incorrectly treated as
stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/tra
vslv and vsrv are broken on little endian, we append 00 to the
high byte not the low byte. Fix it by using the VsrB() accessor.
Signed-off-by: Anton Blanchard
---
target/ppc/int_helper.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/int_helper.c b
The immediate field is 6 bits, not 5.
Fixes: 217f6b88058f ("target-ppc: add dtstsfi[q] instructions")
Signed-off-by: Anton Blanchard
---
target/ppc/internal.h | 2 ++
target/ppc/translate/dfp-impl.inc.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --gi
A recent cleanup changed the pre zeroing of the result from 64 bit
to 32 bit operations:
-result.u64[i] = 0;
+result.VsrW(i) = 0;
This corrupts the result.
Fixes: 60594fea298d ("target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in
int_helper.c")
Signed-off
Hi Alexey,
> Out of curiosity - how did you find this one and (especially) the next
> one - "Fix xxspltib"? Is there some testsuite, or by just looking at
> the code? Thanks,
I'm running test cases and comparing results between QEMU and real
hardware.
Thanks,
Anton
xxspltib raises a VMX or a VSX exception depending on the register
set it is operating on. We had a check, but it was backwards.
Fixes: f113283525a4 ("target-ppc: add xxspltib instruction")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 8
1 file
r the suggestions.
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 68 -
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 4b7627f53b..cdb44b8b70 1
Hi Mark,
> Following on from this I've just gone through the load/store
> operations once again and spotted two things:
>
>
> 1) VSX_LOAD_SCALAR_DS has an extra get_cpu_vsrh() which can be removed
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c index
We were using set_cpu_vsr*() when we should have used get_cpu_vsr*().
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
---
target/ppc/translate/vsx-impl.inc.c | 4 ++--
1 file changed, 2 insert
From: Anton Blanchard
The mcrf emulation code was looking at the CR fields in the reverse
order. It also relied on reserved fields being zero which is somewhat
fragile, so fix that too.
Cc: sta...@vger.kernel.org
Signed-off-by: Anton Blanchard
---
arch/powerpc/lib/sstep.c | 6 --
1 file
From: Anton Blanchard
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
is the wrong size. Fix it.
Signed-off-by: Anton Blanchard
Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
---
target/ppc/arch_dump.c | 2 +-
1 file changed, 1 insertion(+),
Hi Thomas,
> So if you like, I can try to come up with a small patch series that
> cleans up this mess - and I could also include an updated versions of
> Anton's patch there unless he wants to redo the changes on his own...?
Thanks for looking at this. I'm travelling (stuck in an airport at the
Hi,
> From: Benjamin Herrenschmidt
>
> We were always advertising only 4K & 16M. Additionally the code wasn't
> properly matching the page size with the PTE content, which meant we
> could potentially hit an incorrect PTE if the guest used multiple
> sizes.
>
> Finally, honor the CPU capabiliti
From: Anton Blanchard
xsrdpi, xvrdpi and xvrspi use the round ties away method, not round
nearest even.
Signed-off-by: Anton Blanchard
---
target-ppc/fpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index
Hi David,
> I take it float_round_ties_away is the same thing the architecture
> refers to as "round to Nearest Away"?
Yeah. I noticed it when 0.5 got rounded to 0 on QEMU and 1.0 on real
hardware.
Anton
When testing large LMB sizes (eg 4GB), I found a couple of places
that assume they are 32bit in size.
Signed-off-by: Anton Blanchard
---
hw/ppc/spapr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a1b06defe6..0ba2526215 100644
Hi,
> I've now had a bit of time to look through this and I believe it is
> correct, so:
>
> Reviewed-by: Mark Cave-Ayland
Thanks Mark. David: any chance we could get this merged? I can't run a
recent Ubuntu image successfully without it. sshd hangs when I try to
ssh into it.
Thanks,
Anton
vcompress packs vl or less fields into vd, so the tail starts after the
last packed field.
Signed-off-by: Anton Blanchard
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
Hi Alistair,
On Wed, Oct 30, 2024 at 2:39 PM Alistair Francis
wrote:
> > vcompress packs vl or less fields into vd, so the tail starts after the
> > last packed field.
>
> Is that right?
>
> It's different from every other vector command. Although the wording
> in the spec is very confusing
It i
vcompress packs vl or less fields into vd, so the tail starts after the
last packed field. This could be more clearly expressed in the ISA,
but for now this thread helps to explain it:
https://github.com/riscv/riscv-v-spec/issues/796
Signed-off-by: Anton Blanchard
---
target/riscv
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 67
Hi Philippe,
On Sun, Nov 10, 2024 at 5:21 AM Philippe Mathieu-Daudé
wrote:
> Generally speaking (I'm not objecting to this patch as is), for
> DEFINE_VENDOR_CPU() it would be nice to have reference to some
> documentation -- at least to review whether the cpu features
> announced make sense or no
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores.
Signed-off-by: Anton Blanchard
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 67 ++
2 files changed, 68 insertions(+)
diff --git a/target/riscv/cpu
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index bc2780497e..f5ba1c4280 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/target
for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap
because it would mean a register is read with two different SEW
settings.
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index bc22b42801..45b2868c54 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index c66cd95bdb..bc2780497e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
Tenstorrent fork of Whisper which models this
behaviour better than Spike and Sail.
Anton Blanchard (12):
target/riscv: Source vector registers cannot overlap mask register
target/riscv: handle vrgather mask and source overlap
target/riscv: handle vadd.vx form mask and source overlap
target/riscv
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 45b2868c54..2309d9abd0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 312d8b1b81..2741f8bd8e 100644
--- a/target
In these instructions vd is considered a source, so no overlap
is allowed between vd and vs1/vs2. See:
https://github.com/riscv/riscv-isa-manual/issues/1789
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 71 +++--
1 file changed, 56 insertions
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0952bcbe2c..bc22b42801 100644
--- a/target/riscv
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 20b1cb127b..c66cd95bdb 100644
--- a/target/riscv
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f5ba1c4280..a873536eea 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
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