This series fixes some RISC-V instruction corner cases, specifically illegal overlaps between mask and source registers, illegal overlaps between source registers and illegal overlaps between source and destination registers. These were found by looking at miscompares between QEMU and the Tenstorrent fork of Whisper which models this behaviour better than Spike and Sail.
Anton Blanchard (12): target/riscv: Source vector registers cannot overlap mask register target/riscv: handle vrgather mask and source overlap target/riscv: handle vadd.vx form mask and source overlap target/riscv: handle vadd.vv form mask and source overlap target/riscv: handle vslide1down.vx form mask and source overlap target/riscv: handle vzext.vf2 form mask and source overlap target/riscv: handle vwadd.vx form mask and source overlap target/riscv: handle vwadd.vv form mask and source overlap target/riscv: handle vwadd.wv form mask and source overlap target/riscv: handle vwadd.wv form vs1 and vs2 overlap target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS target/riscv: handle overlap in widening instructions with overwrite target/riscv/insn_trans/trans_rvv.c.inc | 139 ++++++++++++++++++------ 1 file changed, 108 insertions(+), 31 deletions(-) -- 2.34.1
